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https://github.com/brain-hackers/u-boot-brain
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f1333417e8
It turns out that the current PCIe reset implementation in the PCIe board init function is not quite working reliably due to PCIe reset timing violations. Fix this by overriding the tegra_pcie_board_port_reset() function. Also allow optionally bringing up the PCIe switch as found on the Apalis Evaluation board. Note however that the Apalis PCIe port is also left disabled in the device tree by default. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
39 lines
777 B
Plaintext
39 lines
777 B
Plaintext
if TARGET_APALIS_TK1
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config SYS_BOARD
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default "apalis-tk1"
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config SYS_VENDOR
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default "toradex"
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config SYS_CONFIG_NAME
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default "apalis-tk1"
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config TDX_CFG_BLOCK
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default y
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config TDX_HAVE_MMC
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default y
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config TDX_CFG_BLOCK_DEV
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default "0"
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config TDX_CFG_BLOCK_PART
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default "1"
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# Toradex config block in eMMC, at the end of 1st "boot sector"
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config TDX_CFG_BLOCK_OFFSET
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default "-512"
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config APALIS_TK1_PCIE_EVALBOARD_INIT
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bool "Apalis Evaluation Board PCIe Initialisation"
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help
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Bring up the Apalis PCIe port with the PCIe switch as found on the
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Apalis Evaluation board. Note that by default the PCIe port is also
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left disabled in the device tree which needs changing as well for this
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to actually work.
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source "board/toradex/common/Kconfig"
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endif
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