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https://github.com/brain-hackers/u-boot-brain
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7682a99826
Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
61 lines
1.2 KiB
ArmAsm
61 lines
1.2 KiB
ArmAsm
/*
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* Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <command.h>
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#include <asm/ppc4xx.h>
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#define CONFIG_405GP 1 /* needed for Linux kernel header files */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#if defined(CONFIG_CMD_KGDB)
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/*
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* cache flushing routines for kgdb
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*/
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.globl kgdb_flush_cache_all
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kgdb_flush_cache_all:
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/* icache */
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iccci r0,r0 /* iccci invalidates the entire I cache */
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/* dcache */
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addi r6,0,0x0000 /* clear GPR 6 */
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addi r7,r0, 128 /* do loop for # of dcache lines */
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/* NOTE: dccci invalidates both */
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mtctr r7 /* ways in the D cache */
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..dcloop:
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dccci 0,r6 /* invalidate line */
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addi r6,r6, 32 /* bump to next line */
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bdnz ..dcloop
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blr
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.globl kgdb_flush_cache_range
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kgdb_flush_cache_range:
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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mr r6,r3
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1: dcbst 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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mtctr r4
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2: icbi 0,r6
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addi r6,r6,L1_CACHE_BYTES
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bdnz 2b
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SYNC
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blr
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#endif
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