mirror of
https://github.com/brain-hackers/u-boot-brain
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2482e3c836
Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
53 lines
1.1 KiB
C
53 lines
1.1 KiB
C
#ifndef __ASM_SH_CACHE_H
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#define __ASM_SH_CACHE_H
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#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
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int cache_control(unsigned int cmd);
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#define L1_CACHE_BYTES 32
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struct __large_struct { unsigned long buf[100]; };
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#define __m(x) (*(struct __large_struct *)(x))
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void dcache_wback_range(u32 start, u32 end)
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{
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u32 v;
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start &= ~(L1_CACHE_BYTES - 1);
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for (v = start; v < end; v += L1_CACHE_BYTES) {
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asm volatile ("ocbwb %0" : /* no output */
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: "m" (__m(v)));
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}
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}
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void dcache_invalid_range(u32 start, u32 end)
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{
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u32 v;
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start &= ~(L1_CACHE_BYTES - 1);
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for (v = start; v < end; v += L1_CACHE_BYTES) {
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asm volatile ("ocbi %0" : /* no output */
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: "m" (__m(v)));
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}
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}
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#else
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/*
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* 32-bytes is the largest L1 data cache line size for SH the architecture. So
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* it is a safe default for DMA alignment.
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*/
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#define ARCH_DMA_MINALIGN 32
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#endif /* CONFIG_SH4 || CONFIG_SH4A */
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/*
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* Use the L1 data cache line size value for the minimum DMA buffer alignment
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* on SH.
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*/
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#ifndef ARCH_DMA_MINALIGN
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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#endif
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#endif /* __ASM_SH_CACHE_H */
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