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https://github.com/brain-hackers/u-boot-brain
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c72f4d4c2e
- Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
17 lines
306 B
C
17 lines
306 B
C
/*
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* Copyright (C) 2016 Socionext Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "../init.h"
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#include "../sc64-regs.h"
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#include "pll.h"
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int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd)
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{
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uniphier_ld20_sscpll_init(SC_DPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
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return 0;
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}
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