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https://github.com/brain-hackers/u-boot-brain
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ee8f0cb3b0
Renesas R8A7795 is CPU with Cortex-a57. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
37 lines
1003 B
C
37 lines
1003 B
C
/*
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* arch/arm/mach-rmobile/include/mach/r8a7795.h
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* This file defines registers and value for r8a7795.
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*
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* Copyright (C) 2015 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_R8A7795_H
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#define __ASM_ARCH_R8A7795_H
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#include "rcar-gen3-base.h"
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/* Module stop control/status register bits */
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#define MSTP0_BITS 0x00640800
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#define MSTP1_BITS 0xF3EE9390
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#define MSTP2_BITS 0x340FAFDC
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#define MSTP3_BITS 0xD80C7CDF
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#define MSTP4_BITS 0x80000184
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#define MSTP5_BITS 0x40BFFF46
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#define MSTP6_BITS 0xE5FBEECF
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#define MSTP7_BITS 0x39FFFF0E
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#define MSTP8_BITS 0x01F19FF4
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#define MSTP9_BITS 0xFFDFFFFF
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#define MSTP10_BITS 0xFFFEFFE0
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#define MSTP11_BITS 0x00000000
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/* SDHI */
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#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
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#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
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#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */
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#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */
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#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
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#endif /* __ASM_ARCH_R8A7795_H */
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