mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-16 07:03:46 +09:00
f0633533d5
The eMMC on sLD3 is assigned with dedicated pins (only multiplexed with GPIO), so it shouldn't hurt to enable eMMC on SPL all the time. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
373 lines
7.8 KiB
Plaintext
373 lines
7.8 KiB
Plaintext
/*
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* Device Tree Source for UniPhier PH1-sLD3 SoC
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*
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* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+ X11
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "socionext,ph1-sld3";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "socionext,uniphier-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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};
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};
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clocks {
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refclk: ref {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24576000>;
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};
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arm_timer_clk: arm_timer_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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uart_clk: uart_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <36864000>;
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};
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iobus_clk: iobus_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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u-boot,dm-pre-reloc;
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timer@20000200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x20000200 0x20>;
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interrupts = <1 11 0x304>;
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clocks = <&arm_timer_clk>;
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};
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timer@20000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x20000600 0x20>;
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interrupts = <1 13 0x304>;
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clocks = <&arm_timer_clk>;
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};
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intc: interrupt-controller@20001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x20001000 0x1000>,
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<0x20000100 0x100>;
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};
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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interrupts = <0 33 4>;
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clocks = <&uart_clk>;
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clock-frequency = <36864000>;
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};
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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interrupts = <0 35 4>;
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clocks = <&uart_clk>;
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clock-frequency = <36864000>;
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};
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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interrupts = <0 37 4>;
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clocks = <&uart_clk>;
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clock-frequency = <36864000>;
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};
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port0x: gpio@55000008 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000008 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port1x: gpio@55000010 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000010 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port2x: gpio@55000018 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000018 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port3x: gpio@55000020 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000020 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port4: gpio@55000028 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000028 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port5x: gpio@55000030 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000030 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port6x: gpio@55000038 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000038 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port7x: gpio@55000040 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000040 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port8x: gpio@55000048 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000048 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port9x: gpio@55000050 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000050 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port10x: gpio@55000058 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000058 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port11x: gpio@55000060 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000060 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port12x: gpio@55000068 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000068 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port13x: gpio@55000070 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000070 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port14x: gpio@55000078 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000078 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port16x: gpio@55000088 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000088 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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i2c0: i2c@58400000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58400000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 1>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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i2c1: i2c@58480000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58480000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 42 1>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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i2c2: i2c@58500000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58500000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 43 1>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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i2c3: i2c@58580000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58580000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 44 1>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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/* chip-internal connection for DMD */
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i2c4: i2c@58600000 {
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compatible = "socionext,uniphier-i2c";
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reg = <0x58600000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 45 1>;
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clocks = <&iobus_clk>;
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clock-frequency = <400000>;
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};
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system_bus: system-bus@58c00000 {
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compatible = "socionext,uniphier-system-bus";
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reg = <0x58c00000 0x400>;
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#address-cells = <2>;
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#size-cells = <1>;
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};
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smpctrl@59800000 {
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compatible = "socionext,uniphier-smpctrl";
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reg = <0x59801000 0x400>;
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};
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mio: mioctrl@59810000 {
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compatible = "socionext,ph1-sld3-mioctrl";
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reg = <0x59810000 0x800>;
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#clock-cells = <1>;
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clock-names = "stdmac", "ehci";
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clocks = <&sysctrl 10>, <&sysctrl 18>;
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};
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emmc: sdhc@5a400000 {
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compatible = "socionext,uniphier-sdhc";
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status = "disabled";
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reg = <0x5a400000 0x200>;
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interrupts = <0 78 4>;
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clocks = <&mio 1>;
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bus-width = <8>;
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non-removable;
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};
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sd: sdhc@5a500000 {
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compatible = "socionext,uniphier-sdhc";
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status = "disabled";
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reg = <0x5a500000 0x200>;
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interrupts = <0 76 4>;
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clocks = <&mio 0>;
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bus-width = <4>;
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};
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usb0: usb@5a800100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a800100 0x100>;
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interrupts = <0 80 4>;
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clocks = <&mio 3>, <&mio 6>;
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};
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usb1: usb@5a810100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a810100 0x100>;
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interrupts = <0 81 4>;
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clocks = <&mio 4>, <&mio 6>;
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};
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usb2: usb@5a820100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a820100 0x100>;
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interrupts = <0 82 4>;
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clocks = <&mio 5>, <&mio 6>;
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};
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usb3: usb@5a830100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a830100 0x100>;
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interrupts = <0 83 4>;
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clocks = <&mio 7>, <&mio 6>;
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};
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aidet@f1830000 {
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compatible = "simple-mfd", "syscon";
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reg = <0xf1830000 0x200>;
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};
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sysctrl: sysctrl@f1840000 {
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compatible = "socionext,ph1-sld3-sysctrl";
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reg = <0xf1840000 0x4000>;
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#clock-cells = <1>;
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clock-names = "ref";
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clocks = <&refclk>;
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};
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nand: nand@f8000000 {
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compatible = "denali,denali-nand-dt";
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reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
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reg-names = "nand_data", "denali_reg";
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};
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};
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};
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