mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-09 11:43:48 +09:00
24357dfd2a
After MMC is converted to DM, convert to use DM SCSI as well for all x86 boards and imply BLK for both MMC and SCSI drivers. CONFIG_SCSI_DEV_LIST is no longer used. Clean them up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
43 lines
855 B
Plaintext
43 lines
855 B
Plaintext
#
|
|
# Copyright (C) 2015 Google, Inc
|
|
#
|
|
# SPDX-License-Identifier: GPL-2.0+
|
|
#
|
|
|
|
config INTEL_BAYTRAIL
|
|
bool
|
|
select HAVE_FSP if !EFI
|
|
select ARCH_MISC_INIT if !EFI
|
|
imply HAVE_INTEL_ME if !EFI
|
|
imply ENABLE_MRC_CACHE
|
|
imply ENV_IS_IN_SPI_FLASH
|
|
imply AHCI_PCI
|
|
imply ICH_SPI
|
|
imply INTEL_ICH6_GPIO
|
|
imply MMC
|
|
imply MMC_PCI
|
|
imply MMC_SDHCI
|
|
imply MMC_SDHCI_SDMA
|
|
imply SCSI
|
|
imply SPI_FLASH
|
|
imply SYS_NS16550
|
|
imply USB
|
|
imply USB_EHCI_HCD
|
|
imply USB_XHCI_HCD
|
|
imply VIDEO_VESA
|
|
|
|
if INTEL_BAYTRAIL
|
|
config INTERNAL_UART
|
|
bool "Enable the SoC integrated legacy UART"
|
|
help
|
|
There is a legacy UART integrated into the Bay Trail SoC.
|
|
A maximum baud rate of 115200 bps is supported. For this
|
|
reason, it is recommended that the UART port be used for
|
|
debug purposes only, eg: U-Boot console.
|
|
|
|
config DEBUG_UART
|
|
bool
|
|
select DEBUG_UART_BOARD_INIT
|
|
|
|
endif
|