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https://github.com/brain-hackers/u-boot-brain
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442e6305b5
Update the devicetree so that the TPM and RTC can be used in SPL. Also enable the pins used for getting the memory configuration settings while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
49 lines
1.1 KiB
C
49 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2017 Intel Corporation.
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* Take from coreboot project file of the same name
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*/
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#ifndef _ASM_ARCH_IOMAP_H
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#define _ASM_ARCH_IOMAP_H
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#define R_ACPI_PM1_TMR 0x8
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/* Put p2sb at 0xd0000000 in TPL */
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#define IOMAP_P2SB_BAR 0xd0000000
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#define IOMAP_P2SB_SIZE 0x10000000
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#define IOMAP_SPI_BASE 0xfe010000
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#define IOMAP_ACPI_BASE 0x400
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#define IOMAP_ACPI_SIZE 0x100
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#define ACPI_BASE_ADDRESS IOMAP_ACPI_BASE
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#define PMC_BAR0 0xfe042000
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#define MCH_BASE_ADDRESS 0xfed10000
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#define MCH_SIZE 0x8000
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#ifdef __ACPI__
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#define HPET_BASE_ADDRESS 0xfed00000
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#define SRAM_BASE_0 0xfe900000
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#define SRAM_SIZE_0 (8 * KiB)
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#define SRAM_BASE_2 0xfe902000
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#define SRAM_SIZE_2 (4 * KiB)
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#endif
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/* Early address for I2C port 2 */
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#define IOMAP_I2C2_BASE (0xfe020000 + 2 * 0x1000)
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/*
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* Use UART2. To use UART1 you need to set '2' to '1', change device tree serial
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* node name and 'reg' property, and update CONFIG_DEBUG_UART_BASE.
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*/
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#define PCH_DEV_UART PCI_BDF(0, 0x18, 2)
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#define PCH_DEV_LPC PCI_BDF(0, 0x1f, 0)
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#define PCH_DEV_SPI PCI_BDF(0, 0x0d, 2)
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#endif
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