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![Eric Nelson](/assets/img/avatar_default.png)
The low four bits of the SYSCTL register are reserved on the USDHC controller on i.MX6 and i.MX7 processors, but are used for clocking operations on earlier models. Guard against their usage by hiding the bit mask macros on those processors. These bits are used to prevent glitches when changing clocks on i.MX35 et al. Use the RSTA bit instead for i.MX6 and i.MX7. >From the i.MX6DQ RM: To prevent possible glitch on the card clock, clear the FRC_SDCLK_ON bit when changing clock divisor value(SDCLKFS or DVS in System Control Register) or setting RSTA bit. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Hector Palacios <hector.palacios@digi.com>
818 lines
21 KiB
C
818 lines
21 KiB
C
/*
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* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
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* Andy Fleming
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*
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* Based vaguely on the pxa mmc code:
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* (C) Copyright 2003
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <hwconfig.h>
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#include <mmc.h>
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#include <part.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <fdt_support.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
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IRQSTATEN_CINT | \
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IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
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IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
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IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
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IRQSTATEN_DINT)
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struct fsl_esdhc {
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uint dsaddr; /* SDMA system address register */
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uint blkattr; /* Block attributes register */
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uint cmdarg; /* Command argument register */
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uint xfertyp; /* Transfer type register */
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uint cmdrsp0; /* Command response 0 register */
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uint cmdrsp1; /* Command response 1 register */
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uint cmdrsp2; /* Command response 2 register */
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uint cmdrsp3; /* Command response 3 register */
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uint datport; /* Buffer data port register */
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uint prsstat; /* Present state register */
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uint proctl; /* Protocol control register */
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uint sysctl; /* System Control Register */
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uint irqstat; /* Interrupt status register */
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uint irqstaten; /* Interrupt status enable register */
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uint irqsigen; /* Interrupt signal enable register */
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uint autoc12err; /* Auto CMD error status register */
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uint hostcapblt; /* Host controller capabilities register */
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uint wml; /* Watermark level register */
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uint mixctrl; /* For USDHC */
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char reserved1[4]; /* reserved */
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uint fevt; /* Force event register */
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uint admaes; /* ADMA error status register */
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uint adsaddr; /* ADMA system address register */
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char reserved2[100]; /* reserved */
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uint vendorspec; /* Vendor Specific register */
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char reserved3[56]; /* reserved */
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uint hostver; /* Host controller version register */
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char reserved4[4]; /* reserved */
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uint dmaerraddr; /* DMA error address register */
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char reserved5[4]; /* reserved */
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uint dmaerrattr; /* DMA error attribute register */
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char reserved6[4]; /* reserved */
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uint hostcapblt2; /* Host controller capabilities register 2 */
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char reserved7[8]; /* reserved */
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uint tcr; /* Tuning control register */
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char reserved8[28]; /* reserved */
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uint sddirctl; /* SD direction control register */
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char reserved9[712]; /* reserved */
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uint scr; /* eSDHC control register */
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};
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/* Return the XFERTYP flags for a given command and data packet */
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static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
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{
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uint xfertyp = 0;
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if (data) {
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xfertyp |= XFERTYP_DPSEL;
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#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
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xfertyp |= XFERTYP_DMAEN;
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#endif
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if (data->blocks > 1) {
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xfertyp |= XFERTYP_MSBSEL;
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xfertyp |= XFERTYP_BCEN;
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#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
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xfertyp |= XFERTYP_AC12EN;
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#endif
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}
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if (data->flags & MMC_DATA_READ)
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xfertyp |= XFERTYP_DTDSEL;
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}
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if (cmd->resp_type & MMC_RSP_CRC)
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xfertyp |= XFERTYP_CCCEN;
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if (cmd->resp_type & MMC_RSP_OPCODE)
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xfertyp |= XFERTYP_CICEN;
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if (cmd->resp_type & MMC_RSP_136)
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xfertyp |= XFERTYP_RSPTYP_136;
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else if (cmd->resp_type & MMC_RSP_BUSY)
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xfertyp |= XFERTYP_RSPTYP_48_BUSY;
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else if (cmd->resp_type & MMC_RSP_PRESENT)
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xfertyp |= XFERTYP_RSPTYP_48;
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#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
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defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE) || \
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defined(CONFIG_PPC_T4160)
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if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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xfertyp |= XFERTYP_CMDTYP_ABORT;
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#endif
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return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
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}
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#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
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/*
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* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
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*/
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static void
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esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
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{
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struct fsl_esdhc_cfg *cfg = mmc->priv;
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struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
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uint blocks;
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char *buffer;
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uint databuf;
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uint size;
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uint irqstat;
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uint timeout;
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if (data->flags & MMC_DATA_READ) {
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blocks = data->blocks;
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buffer = data->dest;
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while (blocks) {
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timeout = PIO_TIMEOUT;
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size = data->blocksize;
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irqstat = esdhc_read32(®s->irqstat);
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while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
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&& --timeout);
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if (timeout <= 0) {
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printf("\nData Read Failed in PIO Mode.");
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return;
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}
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while (size && (!(irqstat & IRQSTAT_TC))) {
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udelay(100); /* Wait before last byte transfer complete */
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irqstat = esdhc_read32(®s->irqstat);
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databuf = in_le32(®s->datport);
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*((uint *)buffer) = databuf;
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buffer += 4;
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size -= 4;
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}
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blocks--;
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}
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} else {
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blocks = data->blocks;
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buffer = (char *)data->src;
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while (blocks) {
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timeout = PIO_TIMEOUT;
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size = data->blocksize;
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irqstat = esdhc_read32(®s->irqstat);
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while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
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&& --timeout);
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if (timeout <= 0) {
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printf("\nData Write Failed in PIO Mode.");
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return;
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}
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while (size && (!(irqstat & IRQSTAT_TC))) {
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udelay(100); /* Wait before last byte transfer complete */
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databuf = *((uint *)buffer);
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buffer += 4;
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size -= 4;
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irqstat = esdhc_read32(®s->irqstat);
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out_le32(®s->datport, databuf);
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}
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blocks--;
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}
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}
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}
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#endif
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static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
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{
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int timeout;
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struct fsl_esdhc_cfg *cfg = mmc->priv;
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struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
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#ifdef CONFIG_FSL_LAYERSCAPE
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dma_addr_t addr;
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#endif
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uint wml_value;
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wml_value = data->blocksize/4;
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if (data->flags & MMC_DATA_READ) {
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if (wml_value > WML_RD_WML_MAX)
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wml_value = WML_RD_WML_MAX_VAL;
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esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
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#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
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#ifdef CONFIG_FSL_LAYERSCAPE
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addr = virt_to_phys((void *)(data->dest));
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if (upper_32_bits(addr))
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printf("Error found for upper 32 bits\n");
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else
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esdhc_write32(®s->dsaddr, lower_32_bits(addr));
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#else
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esdhc_write32(®s->dsaddr, (u32)data->dest);
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#endif
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#endif
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} else {
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#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
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flush_dcache_range((ulong)data->src,
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(ulong)data->src+data->blocks
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*data->blocksize);
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#endif
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if (wml_value > WML_WR_WML_MAX)
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wml_value = WML_WR_WML_MAX_VAL;
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if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
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printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
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return TIMEOUT;
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}
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esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
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wml_value << 16);
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#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
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#ifdef CONFIG_FSL_LAYERSCAPE
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addr = virt_to_phys((void *)(data->src));
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if (upper_32_bits(addr))
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printf("Error found for upper 32 bits\n");
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else
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esdhc_write32(®s->dsaddr, lower_32_bits(addr));
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#else
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esdhc_write32(®s->dsaddr, (u32)data->src);
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#endif
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#endif
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}
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esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
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/* Calculate the timeout period for data transactions */
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/*
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* 1)Timeout period = (2^(timeout+13)) SD Clock cycles
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* 2)Timeout period should be minimum 0.250sec as per SD Card spec
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* So, Number of SD Clock cycles for 0.25sec should be minimum
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* (SD Clock/sec * 0.25 sec) SD Clock cycles
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* = (mmc->clock * 1/4) SD Clock cycles
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* As 1) >= 2)
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* => (2^(timeout+13)) >= mmc->clock * 1/4
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* Taking log2 both the sides
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* => timeout + 13 >= log2(mmc->clock/4)
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* Rounding up to next power of 2
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* => timeout + 13 = log2(mmc->clock/4) + 1
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* => timeout + 13 = fls(mmc->clock/4)
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*/
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timeout = fls(mmc->clock/4);
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timeout -= 13;
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if (timeout > 14)
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timeout = 14;
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if (timeout < 0)
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timeout = 0;
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#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
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if ((timeout == 4) || (timeout == 8) || (timeout == 12))
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timeout++;
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#endif
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#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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timeout = 0xE;
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#endif
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esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
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return 0;
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}
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static void check_and_invalidate_dcache_range
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(struct mmc_cmd *cmd,
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struct mmc_data *data) {
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#ifdef CONFIG_FSL_LAYERSCAPE
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unsigned start = 0;
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#else
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unsigned start = (unsigned)data->dest ;
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#endif
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unsigned size = roundup(ARCH_DMA_MINALIGN,
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data->blocks*data->blocksize);
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unsigned end = start+size ;
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#ifdef CONFIG_FSL_LAYERSCAPE
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dma_addr_t addr;
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addr = virt_to_phys((void *)(data->dest));
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if (upper_32_bits(addr))
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printf("Error found for upper 32 bits\n");
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else
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start = lower_32_bits(addr);
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#endif
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invalidate_dcache_range(start, end);
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}
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/*
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* Sends a command out on the bus. Takes the mmc pointer,
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* a command pointer, and an optional data pointer.
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*/
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static int
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esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
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{
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int err = 0;
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uint xfertyp;
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uint irqstat;
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struct fsl_esdhc_cfg *cfg = mmc->priv;
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volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
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#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
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if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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return 0;
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#endif
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esdhc_write32(®s->irqstat, -1);
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sync();
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/* Wait for the bus to be idle */
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while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
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(esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
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;
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while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
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;
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/* Wait at least 8 SD clock cycles before the next command */
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/*
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* Note: This is way more than 8 cycles, but 1ms seems to
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* resolve timing issues with some cards
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*/
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udelay(1000);
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/* Set up for a data transfer if we have one */
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if (data) {
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err = esdhc_setup_data(mmc, data);
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if(err)
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return err;
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if (data->flags & MMC_DATA_READ)
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check_and_invalidate_dcache_range(cmd, data);
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}
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/* Figure out the transfer arguments */
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xfertyp = esdhc_xfertyp(cmd, data);
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/* Mask all irqs */
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esdhc_write32(®s->irqsigen, 0);
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/* Send the command */
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esdhc_write32(®s->cmdarg, cmd->cmdarg);
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#if defined(CONFIG_FSL_USDHC)
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esdhc_write32(®s->mixctrl,
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(esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
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| (mmc->ddr_mode ? XFERTYP_DDREN : 0));
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esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
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#else
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esdhc_write32(®s->xfertyp, xfertyp);
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#endif
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/* Wait for the command to complete */
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while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
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;
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irqstat = esdhc_read32(®s->irqstat);
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if (irqstat & CMD_ERR) {
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err = COMM_ERR;
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goto out;
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}
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if (irqstat & IRQSTAT_CTOE) {
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err = TIMEOUT;
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goto out;
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}
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/* Switch voltage to 1.8V if CMD11 succeeded */
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if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
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esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
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printf("Run CMD11 1.8V switch\n");
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/* Sleep for 5 ms - max time for card to switch to 1.8V */
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udelay(5000);
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}
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/* Workaround for ESDHC errata ENGcm03648 */
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if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
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int timeout = 6000;
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/* Poll on DATA0 line for cmd with busy signal for 600 ms */
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while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
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PRSSTAT_DAT0)) {
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udelay(100);
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timeout--;
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}
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if (timeout <= 0) {
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printf("Timeout waiting for DAT0 to go high!\n");
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err = TIMEOUT;
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goto out;
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}
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}
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/* Copy the response to the response buffer */
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if (cmd->resp_type & MMC_RSP_136) {
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u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
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cmdrsp3 = esdhc_read32(®s->cmdrsp3);
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cmdrsp2 = esdhc_read32(®s->cmdrsp2);
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cmdrsp1 = esdhc_read32(®s->cmdrsp1);
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cmdrsp0 = esdhc_read32(®s->cmdrsp0);
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cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
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cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
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cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
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cmd->response[3] = (cmdrsp0 << 8);
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} else
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cmd->response[0] = esdhc_read32(®s->cmdrsp0);
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/* Wait until all of the blocks are transferred */
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if (data) {
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#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
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esdhc_pio_read_write(mmc, data);
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#else
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do {
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irqstat = esdhc_read32(®s->irqstat);
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if (irqstat & IRQSTAT_DTOE) {
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err = TIMEOUT;
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goto out;
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}
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if (irqstat & DATA_ERR) {
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err = COMM_ERR;
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goto out;
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}
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} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
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/*
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* Need invalidate the dcache here again to avoid any
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* cache-fill during the DMA operations such as the
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* speculative pre-fetching etc.
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*/
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if (data->flags & MMC_DATA_READ)
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check_and_invalidate_dcache_range(cmd, data);
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#endif
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}
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out:
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/* Reset CMD and DATA portions on error */
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if (err) {
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esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
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SYSCTL_RSTC);
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while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
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;
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if (data) {
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esdhc_write32(®s->sysctl,
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esdhc_read32(®s->sysctl) |
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SYSCTL_RSTD);
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while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
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;
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}
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/* If this was CMD11, then notify that power cycle is needed */
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if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
|
|
printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
|
|
}
|
|
|
|
esdhc_write32(®s->irqstat, -1);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void set_sysctl(struct mmc *mmc, uint clock)
|
|
{
|
|
int div, pre_div;
|
|
struct fsl_esdhc_cfg *cfg = mmc->priv;
|
|
volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
|
|
int sdhc_clk = cfg->sdhc_clk;
|
|
uint clk;
|
|
|
|
if (clock < mmc->cfg->f_min)
|
|
clock = mmc->cfg->f_min;
|
|
|
|
if (sdhc_clk / 16 > clock) {
|
|
for (pre_div = 2; pre_div < 256; pre_div *= 2)
|
|
if ((sdhc_clk / pre_div) <= (clock * 16))
|
|
break;
|
|
} else
|
|
pre_div = 2;
|
|
|
|
for (div = 1; div <= 16; div++)
|
|
if ((sdhc_clk / (div * pre_div)) <= clock)
|
|
break;
|
|
|
|
pre_div >>= mmc->ddr_mode ? 2 : 1;
|
|
div -= 1;
|
|
|
|
clk = (pre_div << 8) | (div << 4);
|
|
|
|
#ifdef CONFIG_FSL_USDHC
|
|
esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
|
|
#else
|
|
esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
|
|
#endif
|
|
|
|
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
|
|
|
|
udelay(10000);
|
|
|
|
#ifdef CONFIG_FSL_USDHC
|
|
esdhc_clrbits32(®s->sysctl, SYSCTL_RSTA);
|
|
#else
|
|
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
|
|
#endif
|
|
|
|
}
|
|
|
|
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
|
static void esdhc_clock_control(struct mmc *mmc, bool enable)
|
|
{
|
|
struct fsl_esdhc_cfg *cfg = mmc->priv;
|
|
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
|
|
u32 value;
|
|
u32 time_out;
|
|
|
|
value = esdhc_read32(®s->sysctl);
|
|
|
|
if (enable)
|
|
value |= SYSCTL_CKEN;
|
|
else
|
|
value &= ~SYSCTL_CKEN;
|
|
|
|
esdhc_write32(®s->sysctl, value);
|
|
|
|
time_out = 20;
|
|
value = PRSSTAT_SDSTB;
|
|
while (!(esdhc_read32(®s->prsstat) & value)) {
|
|
if (time_out == 0) {
|
|
printf("fsl_esdhc: Internal clock never stabilised.\n");
|
|
break;
|
|
}
|
|
time_out--;
|
|
mdelay(1);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static void esdhc_set_ios(struct mmc *mmc)
|
|
{
|
|
struct fsl_esdhc_cfg *cfg = mmc->priv;
|
|
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
|
|
|
|
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
|
/* Select to use peripheral clock */
|
|
esdhc_clock_control(mmc, false);
|
|
esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
|
|
esdhc_clock_control(mmc, true);
|
|
#endif
|
|
/* Set the clock speed */
|
|
set_sysctl(mmc, mmc->clock);
|
|
|
|
/* Set the bus width */
|
|
esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
|
|
|
|
if (mmc->bus_width == 4)
|
|
esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
|
|
else if (mmc->bus_width == 8)
|
|
esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
|
|
|
|
}
|
|
|
|
static int esdhc_init(struct mmc *mmc)
|
|
{
|
|
struct fsl_esdhc_cfg *cfg = mmc->priv;
|
|
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
|
|
int timeout = 1000;
|
|
|
|
/* Reset the entire host controller */
|
|
esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
|
|
|
|
/* Wait until the controller is available */
|
|
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
|
|
udelay(1000);
|
|
|
|
#ifndef ARCH_MXC
|
|
/* Enable cache snooping */
|
|
esdhc_write32(®s->scr, 0x00000040);
|
|
#endif
|
|
|
|
#ifndef CONFIG_FSL_USDHC
|
|
esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
|
|
#endif
|
|
|
|
/* Set the initial clock speed */
|
|
mmc_set_clock(mmc, 400000);
|
|
|
|
/* Disable the BRR and BWR bits in IRQSTAT */
|
|
esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
|
|
|
|
/* Put the PROCTL reg back to the default */
|
|
esdhc_write32(®s->proctl, PROCTL_INIT);
|
|
|
|
/* Set timout to the maximum value */
|
|
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
|
|
|
|
#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
|
|
esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int esdhc_getcd(struct mmc *mmc)
|
|
{
|
|
struct fsl_esdhc_cfg *cfg = mmc->priv;
|
|
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
|
|
int timeout = 1000;
|
|
|
|
#ifdef CONFIG_ESDHC_DETECT_QUIRK
|
|
if (CONFIG_ESDHC_DETECT_QUIRK)
|
|
return 1;
|
|
#endif
|
|
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
|
|
udelay(1000);
|
|
|
|
return timeout > 0;
|
|
}
|
|
|
|
static void esdhc_reset(struct fsl_esdhc *regs)
|
|
{
|
|
unsigned long timeout = 100; /* wait max 100 ms */
|
|
|
|
/* reset the controller */
|
|
esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
|
|
|
|
/* hardware clears the bit when it is done */
|
|
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
|
|
udelay(1000);
|
|
if (!timeout)
|
|
printf("MMC/SD: Reset never completed.\n");
|
|
}
|
|
|
|
static const struct mmc_ops esdhc_ops = {
|
|
.send_cmd = esdhc_send_cmd,
|
|
.set_ios = esdhc_set_ios,
|
|
.init = esdhc_init,
|
|
.getcd = esdhc_getcd,
|
|
};
|
|
|
|
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
|
|
{
|
|
struct fsl_esdhc *regs;
|
|
struct mmc *mmc;
|
|
u32 caps, voltage_caps;
|
|
|
|
if (!cfg)
|
|
return -1;
|
|
|
|
regs = (struct fsl_esdhc *)cfg->esdhc_base;
|
|
|
|
/* First reset the eSDHC controller */
|
|
esdhc_reset(regs);
|
|
|
|
#ifndef CONFIG_FSL_USDHC
|
|
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
|
|
| SYSCTL_IPGEN | SYSCTL_CKEN);
|
|
#endif
|
|
|
|
writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
|
|
memset(&cfg->cfg, 0, sizeof(cfg->cfg));
|
|
|
|
voltage_caps = 0;
|
|
caps = esdhc_read32(®s->hostcapblt);
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
|
|
caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
|
|
ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
|
|
#endif
|
|
|
|
/* T4240 host controller capabilities register should have VS33 bit */
|
|
#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
|
caps = caps | ESDHC_HOSTCAPBLT_VS33;
|
|
#endif
|
|
|
|
if (caps & ESDHC_HOSTCAPBLT_VS18)
|
|
voltage_caps |= MMC_VDD_165_195;
|
|
if (caps & ESDHC_HOSTCAPBLT_VS30)
|
|
voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
|
|
if (caps & ESDHC_HOSTCAPBLT_VS33)
|
|
voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
|
|
cfg->cfg.name = "FSL_SDHC";
|
|
cfg->cfg.ops = &esdhc_ops;
|
|
#ifdef CONFIG_SYS_SD_VOLTAGE
|
|
cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
|
|
#else
|
|
cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
#endif
|
|
if ((cfg->cfg.voltages & voltage_caps) == 0) {
|
|
printf("voltage not supported by controller\n");
|
|
return -1;
|
|
}
|
|
|
|
cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
|
|
#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
|
|
cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
|
|
#endif
|
|
|
|
if (cfg->max_bus_width > 0) {
|
|
if (cfg->max_bus_width < 8)
|
|
cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
|
|
if (cfg->max_bus_width < 4)
|
|
cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
|
|
}
|
|
|
|
if (caps & ESDHC_HOSTCAPBLT_HSS)
|
|
cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
|
|
|
#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
|
|
if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
|
|
cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
|
|
#endif
|
|
|
|
cfg->cfg.f_min = 400000;
|
|
cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);
|
|
|
|
cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
|
|
|
mmc = mmc_create(&cfg->cfg, cfg);
|
|
if (mmc == NULL)
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int fsl_esdhc_mmc_init(bd_t *bis)
|
|
{
|
|
struct fsl_esdhc_cfg *cfg;
|
|
|
|
cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
|
|
cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
|
|
cfg->sdhc_clk = gd->arch.sdhc_clk;
|
|
return fsl_esdhc_initialize(bis, cfg);
|
|
}
|
|
|
|
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
|
|
void mmc_adapter_card_type_ident(void)
|
|
{
|
|
u8 card_id;
|
|
u8 value;
|
|
|
|
card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
|
|
gd->arch.sdhc_adapter = card_id;
|
|
|
|
switch (card_id) {
|
|
case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
|
|
value = QIXIS_READ(brdcfg[5]);
|
|
value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
|
|
QIXIS_WRITE(brdcfg[5], value);
|
|
break;
|
|
case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
|
|
value = QIXIS_READ(pwr_ctl[1]);
|
|
value |= QIXIS_EVDD_BY_SDHC_VS;
|
|
QIXIS_WRITE(pwr_ctl[1], value);
|
|
break;
|
|
case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
|
|
value = QIXIS_READ(brdcfg[5]);
|
|
value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
|
|
QIXIS_WRITE(brdcfg[5], value);
|
|
break;
|
|
case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
|
|
break;
|
|
case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
|
|
break;
|
|
case QIXIS_ESDHC_ADAPTER_TYPE_SD:
|
|
break;
|
|
case QIXIS_ESDHC_NO_ADAPTER:
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_OF_LIBFDT
|
|
void fdt_fixup_esdhc(void *blob, bd_t *bd)
|
|
{
|
|
const char *compat = "fsl,esdhc";
|
|
|
|
#ifdef CONFIG_FSL_ESDHC_PIN_MUX
|
|
if (!hwconfig("esdhc")) {
|
|
do_fixup_by_compat(blob, compat, "status", "disabled",
|
|
8 + 1, 1);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
|
do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
|
|
gd->arch.sdhc_clk, 1);
|
|
#else
|
|
do_fixup_by_compat_u32(blob, compat, "clock-frequency",
|
|
gd->arch.sdhc_clk, 1);
|
|
#endif
|
|
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
|
|
do_fixup_by_compat_u32(blob, compat, "adapter-type",
|
|
(u32)(gd->arch.sdhc_adapter), 1);
|
|
#endif
|
|
do_fixup_by_compat(blob, compat, "status", "okay",
|
|
4 + 1, 1);
|
|
}
|
|
#endif
|