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9606b3c81b
When doing the AT91CAP9/AT91SAM9 port, a number of header files were copied from the Linux kernel sources. This patch explicitly specifies this origin for all the copied headers, and for those missing copyright information, adds it. Additionaly, the header file 'at91sam926x_mc.h' has been superceeded in the latest kernel sources by 'at91sam9_smc.h'. The copyright information has been confirmed by the AT91 Linux kernel maintainer, Andrew Victor <avictor.za@gmail.com>. Signed-off-by: Stelian Pop <stelian@popies.net>
106 lines
4.6 KiB
C
106 lines
4.6 KiB
C
/*
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* [origin: Linux kernel include/asm-arm/arch-at91/at91_spi.h]
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Serial Peripheral Interface (SPI) registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_SPI_H
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#define AT91_SPI_H
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#define AT91_SPI_CR 0x00 /* Control Register */
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#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
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#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
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#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
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#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
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#define AT91_SPI_MR 0x04 /* Mode Register */
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#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
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#define AT91_SPI_PS (1 << 1) /* Peripheral Select */
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#define AT91_SPI_PS_FIXED (0 << 1)
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#define AT91_SPI_PS_VARIABLE (1 << 1)
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#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
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#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
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#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
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#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
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#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
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#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
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#define AT91_SPI_RDR 0x08 /* Receive Data Register */
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#define AT91_SPI_RD (0xffff << 0) /* Receive Data */
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#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
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#define AT91_SPI_TDR 0x0c /* Transmit Data Register */
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#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
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#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
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#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
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#define AT91_SPI_SR 0x10 /* Status Register */
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#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
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#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
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#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
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#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
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#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
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#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
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#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
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#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
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#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
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#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
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#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
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#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
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#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
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#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
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#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
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#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
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#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
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#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
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#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
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#define AT91_SPI_BITS_8 (0 << 4)
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#define AT91_SPI_BITS_9 (1 << 4)
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#define AT91_SPI_BITS_10 (2 << 4)
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#define AT91_SPI_BITS_11 (3 << 4)
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#define AT91_SPI_BITS_12 (4 << 4)
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#define AT91_SPI_BITS_13 (5 << 4)
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#define AT91_SPI_BITS_14 (6 << 4)
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#define AT91_SPI_BITS_15 (7 << 4)
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#define AT91_SPI_BITS_16 (8 << 4)
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#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
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#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
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#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
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#define AT91_SPI_RPR 0x0100 /* Receive Pointer Register */
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#define AT91_SPI_RCR 0x0104 /* Receive Counter Register */
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#define AT91_SPI_TPR 0x0108 /* Transmit Pointer Register */
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#define AT91_SPI_TCR 0x010c /* Transmit Counter Register */
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#define AT91_SPI_RNPR 0x0110 /* Receive Next Pointer Register */
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#define AT91_SPI_RNCR 0x0114 /* Receive Next Counter Register */
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#define AT91_SPI_TNPR 0x0118 /* Transmit Next Pointer Register */
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#define AT91_SPI_TNCR 0x011c /* Transmit Next Counter Register */
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#define AT91_SPI_PTCR 0x0120 /* PDC Transfer Control Register */
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#define AT91_SPI_RXTEN (0x1 << 0) /* Receiver Transfer Enable */
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#define AT91_SPI_RXTDIS (0x1 << 1) /* Receiver Transfer Disable */
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#define AT91_SPI_TXTEN (0x1 << 8) /* Transmitter Transfer Enable */
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#define AT91_SPI_TXTDIS (0x1 << 9) /* Transmitter Transfer Disable */
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#define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */
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#endif
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