mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-01 06:48:52 +09:00
23b5877c64
While the Freescale ARMv8 board LS2085A will enter U-Boot both on a master and a secondary (slave) CPU, this is not the common behaviour on ARMv8 platforms. The norm is that U-Boot is entered from the master CPU only, while the other CPUs are kept in WFI (wait for interrupt) state. The code determining which CPU we are running on is using the MPIDR register, but the definition of that register varies with platform to some extent, and handling multi-cluster platforms (such as the Juno) will become cumbersome. It is better to only enable the multiple entry code on machines that actually need it and disable it by default. Make the single entry default and add a special ARMV8_MULTIENTRY KConfig option to be used by the platforms that need multientry and set it for the LS2085A. Delete all use of the CPU_RELEASE_ADDR from the Vexpress64 boards as it is just totally unused and misleading, and make it conditional in the generic start.S code. This makes the Juno platform start U-Boot properly. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
213 lines
5.0 KiB
C
213 lines
5.0 KiB
C
/*
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* include/asm-arm/macro.h
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*
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* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARM_MACRO_H__
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#define __ASM_ARM_MACRO_H__
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#ifdef __ASSEMBLY__
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/*
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* These macros provide a convenient way to write 8, 16 and 32 bit data
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* to any address.
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* Registers r4 and r5 are used, any data in these registers are
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* overwritten by the macros.
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* The macros are valid for any ARM architecture, they do not implement
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* any memory barriers so caution is recommended when using these when the
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* caches are enabled or on a multi-core system.
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*/
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.macro write32, addr, data
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ldr r4, =\addr
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ldr r5, =\data
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str r5, [r4]
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.endm
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.macro write16, addr, data
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ldr r4, =\addr
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ldrh r5, =\data
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strh r5, [r4]
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.endm
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.macro write8, addr, data
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ldr r4, =\addr
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ldrb r5, =\data
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strb r5, [r4]
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.endm
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/*
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* This macro generates a loop that can be used for delays in the code.
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* Register r4 is used, any data in this register is overwritten by the
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* macro.
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* The macro is valid for any ARM architeture. The actual time spent in the
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* loop will vary from CPU to CPU though.
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*/
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.macro wait_timer, time
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ldr r4, =\time
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1:
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nop
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subs r4, r4, #1
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bcs 1b
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.endm
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#ifdef CONFIG_ARM64
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/*
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* Register aliases.
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*/
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lr .req x30
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/*
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* Branch according to exception level
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*/
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.macro switch_el, xreg, el3_label, el2_label, el1_label
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mrs \xreg, CurrentEL
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cmp \xreg, 0xc
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b.eq \el3_label
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cmp \xreg, 0x8
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b.eq \el2_label
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cmp \xreg, 0x4
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b.eq \el1_label
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.endm
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/*
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* Branch if current processor is a slave,
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* choose processor with all zero affinity value as the master.
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*/
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.macro branch_if_slave, xreg, slave_label
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#ifdef CONFIG_ARMV8_MULTIENTRY
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/* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
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mrs \xreg, mpidr_el1
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tst \xreg, #0xff /* Test Affinity 0 */
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b.ne \slave_label
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lsr \xreg, \xreg, #8
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tst \xreg, #0xff /* Test Affinity 1 */
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b.ne \slave_label
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lsr \xreg, \xreg, #8
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tst \xreg, #0xff /* Test Affinity 2 */
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b.ne \slave_label
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lsr \xreg, \xreg, #16
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tst \xreg, #0xff /* Test Affinity 3 */
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b.ne \slave_label
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#endif
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.endm
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/*
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* Branch if current processor is a master,
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* choose processor with all zero affinity value as the master.
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*/
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.macro branch_if_master, xreg1, xreg2, master_label
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#ifdef CONFIG_ARMV8_MULTIENTRY
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/* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
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mrs \xreg1, mpidr_el1
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lsr \xreg2, \xreg1, #32
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lsl \xreg1, \xreg1, #40
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lsr \xreg1, \xreg1, #40
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orr \xreg1, \xreg1, \xreg2
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cbz \xreg1, \master_label
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#else
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b \master_label
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#endif
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.endm
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.macro armv8_switch_to_el2_m, xreg1
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/* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
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mov \xreg1, #0x5b1
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msr scr_el3, \xreg1
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msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
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mov \xreg1, #0x33ff
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msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */
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/* Initialize SCTLR_EL2
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*
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* setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
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* and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) +
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* EE,WXN,I,SA,C,A,M to 0
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*/
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mov \xreg1, #0x0830
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movk \xreg1, #0x30C5, lsl #16
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msr sctlr_el2, \xreg1
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/* Return to the EL2_SP2 mode from EL3 */
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mov \xreg1, sp
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msr sp_el2, \xreg1 /* Migrate SP */
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mrs \xreg1, vbar_el3
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msr vbar_el2, \xreg1 /* Migrate VBAR */
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mov \xreg1, #0x3c9
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msr spsr_el3, \xreg1 /* EL2_SP2 | D | A | I | F */
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msr elr_el3, lr
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eret
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.endm
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.macro armv8_switch_to_el1_m, xreg1, xreg2
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/* Initialize Generic Timers */
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mrs \xreg1, cnthctl_el2
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orr \xreg1, \xreg1, #0x3 /* Enable EL1 access to timers */
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msr cnthctl_el2, \xreg1
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msr cntvoff_el2, xzr
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/* Initilize MPID/MPIDR registers */
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mrs \xreg1, midr_el1
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mrs \xreg2, mpidr_el1
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msr vpidr_el2, \xreg1
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msr vmpidr_el2, \xreg2
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/* Disable coprocessor traps */
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mov \xreg1, #0x33ff
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msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */
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msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
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mov \xreg1, #3 << 20
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msr cpacr_el1, \xreg1 /* Enable FP/SIMD at EL1 */
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/* Initialize HCR_EL2 */
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mov \xreg1, #(1 << 31) /* 64bit EL1 */
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orr \xreg1, \xreg1, #(1 << 29) /* Disable HVC */
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msr hcr_el2, \xreg1
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/* SCTLR_EL1 initialization
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*
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* setting RES1 bits (29,28,23,22,20,11) to 1
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* and RES0 bits (31,30,27,21,17,13,10,6) +
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* UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD,
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* CP15BEN,SA0,SA,C,A,M to 0
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*/
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mov \xreg1, #0x0800
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movk \xreg1, #0x30d0, lsl #16
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msr sctlr_el1, \xreg1
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/* Return to the EL1_SP1 mode from EL2 */
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mov \xreg1, sp
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msr sp_el1, \xreg1 /* Migrate SP */
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mrs \xreg1, vbar_el2
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msr vbar_el1, \xreg1 /* Migrate VBAR */
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mov \xreg1, #0x3c5
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msr spsr_el2, \xreg1 /* EL1_SP1 | D | A | I | F */
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msr elr_el2, lr
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eret
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.endm
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#if defined(CONFIG_GICV3)
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.macro gic_wait_for_interrupt_m xreg1
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0 : wfi
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mrs \xreg1, ICC_IAR1_EL1
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msr ICC_EOIR1_EL1, \xreg1
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cbnz \xreg1, 0b
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.endm
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#elif defined(CONFIG_GICV2)
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.macro gic_wait_for_interrupt_m xreg1, wreg2
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0 : wfi
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ldr \wreg2, [\xreg1, GICC_AIAR]
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str \wreg2, [\xreg1, GICC_AEOIR]
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and \wreg2, \wreg2, #0x3ff
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cbnz \wreg2, 0b
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.endm
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#endif
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#endif /* CONFIG_ARM64 */
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARM_MACRO_H__ */
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