mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-24 11:59:46 +09:00
23b5877c64
While the Freescale ARMv8 board LS2085A will enter U-Boot both on a master and a secondary (slave) CPU, this is not the common behaviour on ARMv8 platforms. The norm is that U-Boot is entered from the master CPU only, while the other CPUs are kept in WFI (wait for interrupt) state. The code determining which CPU we are running on is using the MPIDR register, but the definition of that register varies with platform to some extent, and handling multi-cluster platforms (such as the Juno) will become cumbersome. It is better to only enable the multiple entry code on machines that actually need it and disable it by default. Make the single entry default and add a special ARMV8_MULTIENTRY KConfig option to be used by the platforms that need multientry and set it for the LS2085A. Delete all use of the CPU_RELEASE_ADDR from the Vexpress64 boards as it is just totally unused and misleading, and make it conditional in the generic start.S code. This makes the Juno platform start U-Boot properly. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
182 lines
3.6 KiB
ArmAsm
182 lines
3.6 KiB
ArmAsm
/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <version.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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#include <asm/armv8/mmu.h>
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/*************************************************************************
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*
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* Startup Code (reset vector)
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*
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*************************************************************************/
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.globl _start
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_start:
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b reset
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.align 3
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.globl _TEXT_BASE
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_TEXT_BASE:
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.quad CONFIG_SYS_TEXT_BASE
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/*
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* These are defined in the linker script.
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*/
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.globl _end_ofs
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_end_ofs:
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.quad _end - _start
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.globl _bss_start_ofs
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_bss_start_ofs:
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.quad __bss_start - _start
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.globl _bss_end_ofs
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_bss_end_ofs:
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.quad __bss_end - _start
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reset:
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/*
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* Could be EL3/EL2/EL1, Initial State:
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* Little Endian, MMU Disabled, i/dCache Disabled
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*/
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adr x0, vectors
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switch_el x1, 3f, 2f, 1f
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3: msr vbar_el3, x0
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mrs x0, scr_el3
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orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
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msr scr_el3, x0
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msr cptr_el3, xzr /* Enable FP/SIMD */
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ldr x0, =COUNTER_FREQUENCY
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msr cntfrq_el0, x0 /* Initialize CNTFRQ */
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b 0f
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2: msr vbar_el2, x0
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mov x0, #0x33ff
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msr cptr_el2, x0 /* Enable FP/SIMD */
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b 0f
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1: msr vbar_el1, x0
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mov x0, #3 << 20
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msr cpacr_el1, x0 /* Enable FP/SIMD */
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0:
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/*
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* Cache/BPB/TLB Invalidate
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* i-cache is invalidated before enabled in icache_enable()
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* tlb is invalidated before mmu is enabled in dcache_enable()
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* d-cache is invalidated before enabled in dcache_enable()
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*/
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/* Processor specific initialization */
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bl lowlevel_init
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#ifdef CONFIG_ARMV8_MULTIENTRY
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branch_if_master x0, x1, master_cpu
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/*
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* Slave CPUs
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*/
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slave_cpu:
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wfe
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ldr x1, =CPU_RELEASE_ADDR
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ldr x0, [x1]
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cbz x0, slave_cpu
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br x0 /* branch to the given address */
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master_cpu:
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/* On the master CPU */
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#endif /* CONFIG_ARMV8_MULTIENTRY */
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bl _main
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/*-----------------------------------------------------------------------*/
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WEAK(lowlevel_init)
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mov x29, lr /* Save LR */
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#ifndef CONFIG_ARMV8_MULTIENTRY
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/*
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* For single-entry systems the lowlevel init is very simple.
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*/
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ldr x0, =GICD_BASE
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bl gic_init_secure
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#else /* CONFIG_ARMV8_MULTIENTRY is set */
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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branch_if_slave x0, 1f
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ldr x0, =GICD_BASE
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bl gic_init_secure
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1:
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#if defined(CONFIG_GICV3)
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ldr x0, =GICR_BASE
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bl gic_init_secure_percpu
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#elif defined(CONFIG_GICV2)
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ldr x0, =GICD_BASE
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ldr x1, =GICC_BASE
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bl gic_init_secure_percpu
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#endif
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#endif
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branch_if_master x0, x1, 2f
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/*
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* Slave should wait for master clearing spin table.
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* This sync prevent salves observing incorrect
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* value of spin table and jumping to wrong place.
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*/
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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#ifdef CONFIG_GICV2
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ldr x0, =GICC_BASE
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#endif
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bl gic_wait_for_interrupt
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#endif
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/*
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* All slaves will enter EL2 and optionally EL1.
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*/
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bl armv8_switch_to_el2
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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bl armv8_switch_to_el1
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#endif
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#endif /* CONFIG_ARMV8_MULTIENTRY */
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2:
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mov lr, x29 /* Restore LR */
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ret
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ENDPROC(lowlevel_init)
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WEAK(smp_kick_all_cpus)
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/* Kick secondary cpus up by SGI 0 interrupt */
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mov x29, lr /* Save LR */
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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ldr x0, =GICD_BASE
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bl gic_kick_secondary_cpus
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#endif
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mov lr, x29 /* Restore LR */
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ret
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ENDPROC(smp_kick_all_cpus)
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/*-----------------------------------------------------------------------*/
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ENTRY(c_runtime_cpu_setup)
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/* Relocate vBAR */
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adr x0, vectors
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switch_el x1, 3f, 2f, 1f
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3: msr vbar_el3, x0
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b 0f
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2: msr vbar_el2, x0
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b 0f
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1: msr vbar_el1, x0
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0:
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ret
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ENDPROC(c_runtime_cpu_setup)
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