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https://github.com/brain-hackers/u-boot-brain
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239cb9d904
This commit is based on that patch from aaron.williams@caviumnetworks.com with same commit title. pulled the same code changes into current u-boot tree. http://patchwork.ozlabs.org/patch/140863/ http://lists.denx.de/pipermail/u-boot/2011-April/089606.html This patch corrects the addresses used when working with Spansion/AMD FLASH chips. Addressing for 8 and 16 bits is almost identical except in the 16-bit case the LSB of the address is always 0. The confusion arose because the addresses in the datasheet for 16-bit mode are word addresses but this code assumed it was byte addresses. I have only been able to test this on our Octeon boards which use either an 8-bit or 16-bit bus. I have not tested the case where there's an 8-bit part on a 16-bit bus. This patch also adds some delays as suggested by Spansion. If a part can be both 8 and 16-bits, it forces it to work in 8-bit mode if an 8-bit bus is detected. Apart from the pulled changes, fixed few minor code cleanups and tested on 256M29EW, 512M29EW flashes. Before this fix: --------------- Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0xFF, Device ID: 0xFF Erase timeout: 4096 ms, write timeout: 2 ms Buffer write timeout: 5 ms, buffer size: 1024 bytes After this fix: -------------- Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0x89, Device ID: 0x7E2301 Erase timeout: 4096 ms, write timeout: 2 ms Buffer write timeout: 5 ms, buffer size: 1024 bytes Signed-off-by: Aaron Williams <aaron.williams@caviumnetworks.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
186 lines
5.5 KiB
C
186 lines
5.5 KiB
C
/*
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* (C) Copyright 2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef __CFI_FLASH_H__
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#define __CFI_FLASH_H__
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#define FLASH_CMD_CFI 0x98
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#define FLASH_CMD_READ_ID 0x90
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#define FLASH_CMD_RESET 0xff
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#define FLASH_CMD_BLOCK_ERASE 0x20
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#define FLASH_CMD_ERASE_CONFIRM 0xD0
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#define FLASH_CMD_WRITE 0x40
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#define FLASH_CMD_PROTECT 0x60
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#define FLASH_CMD_SETUP 0x60
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#define FLASH_CMD_SET_CR_CONFIRM 0x03
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#define FLASH_CMD_PROTECT_SET 0x01
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#define FLASH_CMD_PROTECT_CLEAR 0xD0
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#define FLASH_CMD_CLEAR_STATUS 0x50
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#define FLASH_CMD_READ_STATUS 0x70
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#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
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#define FLASH_CMD_WRITE_BUFFER_PROG 0xE9
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#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
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#define FLASH_STATUS_DONE 0x80
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#define FLASH_STATUS_ESS 0x40
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#define FLASH_STATUS_ECLBS 0x20
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#define FLASH_STATUS_PSLBS 0x10
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#define FLASH_STATUS_VPENS 0x08
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#define FLASH_STATUS_PSS 0x04
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#define FLASH_STATUS_DPS 0x02
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#define FLASH_STATUS_R 0x01
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#define FLASH_STATUS_PROTECT 0x01
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#define AMD_CMD_RESET 0xF0
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#define AMD_CMD_WRITE 0xA0
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#define AMD_CMD_ERASE_START 0x80
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#define AMD_CMD_ERASE_SECTOR 0x30
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#define AMD_CMD_UNLOCK_START 0xAA
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#define AMD_CMD_UNLOCK_ACK 0x55
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#define AMD_CMD_WRITE_TO_BUFFER 0x25
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#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29
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#define AMD_CMD_SET_PPB_ENTRY 0xC0
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#define AMD_CMD_SET_PPB_EXIT_BC1 0x90
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#define AMD_CMD_SET_PPB_EXIT_BC2 0x00
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#define AMD_CMD_PPB_UNLOCK_BC1 0x80
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#define AMD_CMD_PPB_UNLOCK_BC2 0x30
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#define AMD_CMD_PPB_LOCK_BC1 0xA0
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#define AMD_CMD_PPB_LOCK_BC2 0x00
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#define AMD_STATUS_TOGGLE 0x40
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#define AMD_STATUS_ERROR 0x20
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#define ATM_CMD_UNLOCK_SECT 0x70
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#define ATM_CMD_SOFTLOCK_START 0x80
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#define ATM_CMD_LOCK_SECT 0x40
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#define FLASH_CONTINUATION_CODE 0x7F
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#define FLASH_OFFSET_MANUFACTURER_ID 0x00
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#define FLASH_OFFSET_DEVICE_ID 0x02
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#define FLASH_OFFSET_DEVICE_ID2 0x1C
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#define FLASH_OFFSET_DEVICE_ID3 0x1E
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#define FLASH_OFFSET_CFI 0xAA
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#define FLASH_OFFSET_CFI_ALT 0x555
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#define FLASH_OFFSET_CFI_RESP 0x20
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#define FLASH_OFFSET_PRIMARY_VENDOR 0x26
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/* extended query table primary address */
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#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x2A
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#define FLASH_OFFSET_WTOUT 0x1F
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#define FLASH_OFFSET_WBTOUT 0x40
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#define FLASH_OFFSET_ETOUT 0x4A
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#define FLASH_OFFSET_CETOUT 0x44
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#define FLASH_OFFSET_WMAX_TOUT 0x46
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#define FLASH_OFFSET_WBMAX_TOUT 0x48
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#define FLASH_OFFSET_EMAX_TOUT 0x4A
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#define FLASH_OFFSET_CEMAX_TOUT 0x4C
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#define FLASH_OFFSET_SIZE 0x4E
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#define FLASH_OFFSET_INTERFACE 0x50
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#define FLASH_OFFSET_BUFFER_SIZE 0x54
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#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x58
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#define FLASH_OFFSET_ERASE_REGIONS 0x5A
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#define FLASH_OFFSET_PROTECT 0x04
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#define FLASH_OFFSET_USER_PROTECTION 0x85
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#define FLASH_OFFSET_INTEL_PROTECTION 0x81
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#define CFI_CMDSET_NONE 0
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#define CFI_CMDSET_INTEL_EXTENDED 1
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#define CFI_CMDSET_AMD_STANDARD 2
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#define CFI_CMDSET_INTEL_STANDARD 3
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#define CFI_CMDSET_AMD_EXTENDED 4
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#define CFI_CMDSET_MITSU_STANDARD 256
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#define CFI_CMDSET_MITSU_EXTENDED 257
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#define CFI_CMDSET_SST 258
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#define CFI_CMDSET_INTEL_PROG_REGIONS 512
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#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
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# undef FLASH_CMD_RESET
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# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
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#endif
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#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */
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typedef union {
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unsigned char c;
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unsigned short w;
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unsigned long l;
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unsigned long long ll;
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} cfiword_t;
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/* CFI standard query structure */
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struct cfi_qry {
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u8 qry[3];
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u16 p_id;
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u16 p_adr;
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u16 a_id;
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u16 a_adr;
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u8 vcc_min;
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u8 vcc_max;
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u8 vpp_min;
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u8 vpp_max;
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u8 word_write_timeout_typ;
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u8 buf_write_timeout_typ;
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u8 block_erase_timeout_typ;
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u8 chip_erase_timeout_typ;
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u8 word_write_timeout_max;
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u8 buf_write_timeout_max;
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u8 block_erase_timeout_max;
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u8 chip_erase_timeout_max;
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u8 dev_size;
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u16 interface_desc;
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u16 max_buf_write_size;
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u8 num_erase_regions;
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u32 erase_region_info[NUM_ERASE_REGIONS];
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} __attribute__((packed));
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struct cfi_pri_hdr {
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u8 pri[3];
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u8 major_version;
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u8 minor_version;
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} __attribute__((packed));
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#ifndef CONFIG_SYS_FLASH_BANKS_LIST
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#endif
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/*
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* CFI_MAX_FLASH_BANKS only used for flash_info struct declaration.
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*
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* Use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined
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*/
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#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
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#define CONFIG_SYS_MAX_FLASH_BANKS (cfi_flash_num_flash_banks)
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#define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT
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/* board code can update this variable before CFI detection */
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extern int cfi_flash_num_flash_banks;
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#else
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#define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS
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#endif
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void flash_write_cmd(flash_info_t * info, flash_sect_t sect,
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uint offset, u32 cmd);
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#endif /* __CFI_FLASH_H__ */
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