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https://github.com/brain-hackers/u-boot-brain
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fd40ad0d57
The Allwinner H6 SoC uses a quite different memory map, also changes the clocks quite a bit. This requires some changes to the SPL SPI routine, which hardcodes these values so far. Using the just introduced helper functions to determine base address and SPI controller generation, we can cover some of these differences easily. The clock setup is different, so requires some explicit code changes there (reset and clock gate in one register at a different address). Also we need to change the pinmux function to use a different set of pins that the H6 uses for SPI0. Eventually we can enable the H6 to use SPI booting in Kconfig. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
357 lines
10 KiB
C
357 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com>
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <linux/libfdt.h>
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#ifdef CONFIG_SPL_OS_BOOT
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#error CONFIG_SPL_OS_BOOT is not supported yet
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#endif
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/*
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* This is a very simple U-Boot image loading implementation, trying to
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* replicate what the boot ROM is doing when loading the SPL. Because we
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* know the exact pins where the SPI Flash is connected and also know
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* that the Read Data Bytes (03h) command is supported, the hardware
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* configuration is very simple and we don't need the extra flexibility
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* of the SPI framework. Moreover, we rely on the default settings of
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* the SPI controler hardware registers and only adjust what needs to
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* be changed. This is good for the code size and this implementation
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* adds less than 400 bytes to the SPL.
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*
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* There are two variants of the SPI controller in Allwinner SoCs:
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* A10/A13/A20 (sun4i variant) and everything else (sun6i variant).
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* Both of them are supported.
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*
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* The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are
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* supported at the moment.
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*/
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/*****************************************************************************/
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/* SUN4I variant of the SPI controller */
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/*****************************************************************************/
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#define SUN4I_SPI0_CCTL 0x1C
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#define SUN4I_SPI0_CTL 0x08
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#define SUN4I_SPI0_RX 0x00
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#define SUN4I_SPI0_TX 0x04
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#define SUN4I_SPI0_FIFO_STA 0x28
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#define SUN4I_SPI0_BC 0x20
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#define SUN4I_SPI0_TC 0x24
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#define SUN4I_CTL_ENABLE BIT(0)
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#define SUN4I_CTL_MASTER BIT(1)
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#define SUN4I_CTL_TF_RST BIT(8)
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#define SUN4I_CTL_RF_RST BIT(9)
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#define SUN4I_CTL_XCH BIT(10)
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/*****************************************************************************/
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/* SUN6I variant of the SPI controller */
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/*****************************************************************************/
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#define SUN6I_SPI0_CCTL 0x24
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#define SUN6I_SPI0_GCR 0x04
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#define SUN6I_SPI0_TCR 0x08
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#define SUN6I_SPI0_FIFO_STA 0x1C
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#define SUN6I_SPI0_MBC 0x30
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#define SUN6I_SPI0_MTC 0x34
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#define SUN6I_SPI0_BCC 0x38
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#define SUN6I_SPI0_TXD 0x200
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#define SUN6I_SPI0_RXD 0x300
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#define SUN6I_CTL_ENABLE BIT(0)
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#define SUN6I_CTL_MASTER BIT(1)
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#define SUN6I_CTL_SRST BIT(31)
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#define SUN6I_TCR_XCH BIT(31)
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/*****************************************************************************/
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#define CCM_AHB_GATING0 (0x01C20000 + 0x60)
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#define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c)
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#ifdef CONFIG_MACH_SUN50I_H6
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#define CCM_SPI0_CLK (0x03001000 + 0x940)
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#else
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#define CCM_SPI0_CLK (0x01C20000 + 0xA0)
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#endif
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#define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0)
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#define AHB_RESET_SPI0_SHIFT 20
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#define AHB_GATE_OFFSET_SPI0 20
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#define SPI0_CLK_DIV_BY_2 0x1000
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#define SPI0_CLK_DIV_BY_4 0x1001
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/*****************************************************************************/
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/*
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* Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
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* from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
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* The H6 uses PC0, PC2, PC3, PC5.
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*/
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static void spi0_pinmux_setup(unsigned int pin_function)
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{
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/* All chips use PC0 and PC2. */
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sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
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sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
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/* All chips except H6 use PC1, and only H6 uses PC5. */
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if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
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sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function);
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else
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sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
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/* Older generations use PC23 for CS, newer ones use PC3. */
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if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) ||
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IS_ENABLED(CONFIG_MACH_SUN8I_R40))
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sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
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else
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sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
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}
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static bool is_sun6i_gen_spi(void)
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{
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return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
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IS_ENABLED(CONFIG_MACH_SUN50I_H6);
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}
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static uintptr_t spi0_base_address(void)
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{
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if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
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return 0x01C05000;
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if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
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return 0x05010000;
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if (!is_sun6i_gen_spi())
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return 0x01C05000;
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return 0x01C68000;
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}
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/*
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* Setup 6 MHz from OSC24M (because the BROM is doing the same).
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*/
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static void spi0_enable_clock(void)
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{
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uintptr_t base = spi0_base_address();
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/* Deassert SPI0 reset on SUN6I */
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if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
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setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
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else if (is_sun6i_gen_spi())
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setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
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(1 << AHB_RESET_SPI0_SHIFT));
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/* Open the SPI0 gate */
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if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
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setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
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/* Divide by 4 */
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writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
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SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
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/* 24MHz from OSC24M */
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writel((1 << 31), CCM_SPI0_CLK);
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if (is_sun6i_gen_spi()) {
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/* Enable SPI in the master mode and do a soft reset */
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setbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
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SUN6I_CTL_ENABLE | SUN6I_CTL_SRST);
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/* Wait for completion */
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while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
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;
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} else {
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/* Enable SPI in the master mode and reset FIFO */
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setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
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SUN4I_CTL_ENABLE |
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SUN4I_CTL_TF_RST |
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SUN4I_CTL_RF_RST);
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}
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}
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static void spi0_disable_clock(void)
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{
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uintptr_t base = spi0_base_address();
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/* Disable the SPI0 controller */
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if (is_sun6i_gen_spi())
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clrbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
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SUN6I_CTL_ENABLE);
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else
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clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
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SUN4I_CTL_ENABLE);
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/* Disable the SPI0 clock */
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writel(0, CCM_SPI0_CLK);
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/* Close the SPI0 gate */
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if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
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clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
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/* Assert SPI0 reset on SUN6I */
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if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
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clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
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else if (is_sun6i_gen_spi())
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clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
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(1 << AHB_RESET_SPI0_SHIFT));
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}
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static void spi0_init(void)
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{
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unsigned int pin_function = SUNXI_GPC_SPI0;
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if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
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IS_ENABLED(CONFIG_MACH_SUN50I_H6))
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pin_function = SUN50I_GPC_SPI0;
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spi0_pinmux_setup(pin_function);
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spi0_enable_clock();
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}
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static void spi0_deinit(void)
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{
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/* New SoCs can disable pins, older could only set them as input */
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unsigned int pin_function = SUNXI_GPIO_INPUT;
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if (is_sun6i_gen_spi())
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pin_function = SUNXI_GPIO_DISABLE;
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spi0_disable_clock();
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spi0_pinmux_setup(pin_function);
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}
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/*****************************************************************************/
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#define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */
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static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,
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ulong spi_ctl_reg,
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ulong spi_ctl_xch_bitmask,
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ulong spi_fifo_reg,
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ulong spi_tx_reg,
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ulong spi_rx_reg,
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ulong spi_bc_reg,
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ulong spi_tc_reg,
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ulong spi_bcc_reg)
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{
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writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */
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writel(4, spi_tc_reg); /* Transfer counter (bytes to send) */
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if (spi_bcc_reg)
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writel(4, spi_bcc_reg); /* SUN6I also needs this */
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/* Send the Read Data Bytes (03h) command header */
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writeb(0x03, spi_tx_reg);
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writeb((u8)(addr >> 16), spi_tx_reg);
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writeb((u8)(addr >> 8), spi_tx_reg);
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writeb((u8)(addr), spi_tx_reg);
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/* Start the data transfer */
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setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask);
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/* Wait until everything is received in the RX FIFO */
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while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize)
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;
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/* Skip 4 bytes */
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readl(spi_rx_reg);
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/* Read the data */
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while (bufsize-- > 0)
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*buf++ = readb(spi_rx_reg);
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/* tSHSL time is up to 100 ns in various SPI flash datasheets */
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udelay(1);
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}
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static void spi0_read_data(void *buf, u32 addr, u32 len)
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{
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u8 *buf8 = buf;
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u32 chunk_len;
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uintptr_t base = spi0_base_address();
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while (len > 0) {
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chunk_len = len;
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if (chunk_len > SPI_READ_MAX_SIZE)
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chunk_len = SPI_READ_MAX_SIZE;
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if (is_sun6i_gen_spi()) {
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sunxi_spi0_read_data(buf8, addr, chunk_len,
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base + SUN6I_SPI0_TCR,
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SUN6I_TCR_XCH,
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base + SUN6I_SPI0_FIFO_STA,
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base + SUN6I_SPI0_TXD,
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base + SUN6I_SPI0_RXD,
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base + SUN6I_SPI0_MBC,
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base + SUN6I_SPI0_MTC,
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base + SUN6I_SPI0_BCC);
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} else {
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sunxi_spi0_read_data(buf8, addr, chunk_len,
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base + SUN4I_SPI0_CTL,
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SUN4I_CTL_XCH,
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base + SUN4I_SPI0_FIFO_STA,
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base + SUN4I_SPI0_TX,
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base + SUN4I_SPI0_RX,
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base + SUN4I_SPI0_BC,
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base + SUN4I_SPI0_TC,
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0);
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}
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len -= chunk_len;
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buf8 += chunk_len;
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addr += chunk_len;
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}
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}
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static ulong spi_load_read(struct spl_load_info *load, ulong sector,
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ulong count, void *buf)
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{
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spi0_read_data(buf, sector, count);
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return count;
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}
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/*****************************************************************************/
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static int spl_spi_load_image(struct spl_image_info *spl_image,
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struct spl_boot_device *bootdev)
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{
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int ret = 0;
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struct image_header *header;
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header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
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spi0_init();
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spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40);
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if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
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image_get_magic(header) == FDT_MAGIC) {
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struct spl_load_info load;
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debug("Found FIT image\n");
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load.dev = NULL;
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load.priv = NULL;
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load.filename = NULL;
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load.bl_len = 1;
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load.read = spi_load_read;
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ret = spl_load_simple_fit(spl_image, &load,
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CONFIG_SYS_SPI_U_BOOT_OFFS, header);
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} else {
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ret = spl_parse_image_header(spl_image, header);
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if (ret)
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return ret;
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spi0_read_data((void *)spl_image->load_addr,
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CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image->size);
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}
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spi0_deinit();
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return ret;
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}
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/* Use priorty 0 to override the default if it happens to be linked in */
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SPL_LOAD_IMAGE_METHOD("sunxi SPI", 0, BOOT_DEVICE_SPI, spl_spi_load_image);
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