669 lines
18 KiB
C
669 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
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*/
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#include <kendryte/clk.h>
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#include <asm/io.h>
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#include <dt-bindings/clock/k210-sysctl.h>
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#include <dt-bindings/mfd/k210-sysctl.h>
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#include <dm.h>
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#include <log.h>
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#include <mapmem.h>
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#include <kendryte/bypass.h>
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#include <kendryte/pll.h>
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/* All methods are delegated to CCF clocks */
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static ulong k210_clk_get_rate(struct clk *clk)
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{
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struct clk *c;
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int err = clk_get_by_id(clk->id, &c);
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if (err)
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return err;
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return clk_get_rate(c);
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}
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static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate)
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{
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struct clk *c;
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int err = clk_get_by_id(clk->id, &c);
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if (err)
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return err;
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return clk_set_rate(c, rate);
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}
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static int k210_clk_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk *c, *p;
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int err = clk_get_by_id(clk->id, &c);
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if (err)
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return err;
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err = clk_get_by_id(parent->id, &p);
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if (err)
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return err;
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return clk_set_parent(c, p);
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}
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static int k210_clk_endisable(struct clk *clk, bool enable)
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{
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struct clk *c;
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int err = clk_get_by_id(clk->id, &c);
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if (err)
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return err;
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return enable ? clk_enable(c) : clk_disable(c);
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}
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static int k210_clk_enable(struct clk *clk)
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{
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return k210_clk_endisable(clk, true);
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}
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static int k210_clk_disable(struct clk *clk)
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{
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return k210_clk_endisable(clk, false);
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}
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static const struct clk_ops k210_clk_ops = {
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.set_rate = k210_clk_set_rate,
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.get_rate = k210_clk_get_rate,
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.set_parent = k210_clk_set_parent,
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.enable = k210_clk_enable,
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.disable = k210_clk_disable,
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};
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/* Parents for muxed clocks */
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static const char * const generic_sels[] = { "in0_half", "pll0_half" };
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/* The first clock is in0, which is filled in by k210_clk_probe */
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static const char *aclk_sels[] = { NULL, "pll0_half" };
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static const char *pll2_sels[] = { NULL, "pll0", "pll1" };
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/*
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* All parameters for different sub-clocks are collected into parameter arrays.
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* These parameters are then initialized by the clock which uses them during
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* probe. To save space, ids are automatically generated for each sub-clock by
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* using an enum. Instead of storing a parameter struct for each clock, even for
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* those clocks which don't use a particular type of sub-clock, we can just
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* store the parameters for the clocks which need them.
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*
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* So why do it like this? Arranging all the sub-clocks together makes it very
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* easy to find bugs in the code.
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*/
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#define DIV(id, off, shift, width) DIV_FLAGS(id, off, shift, width, 0)
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#define DIV_LIST \
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DIV_FLAGS(K210_CLK_ACLK, K210_SYSCTL_SEL0, 1, 2, \
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CLK_DIVIDER_POWER_OF_TWO) \
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DIV(K210_CLK_APB0, K210_SYSCTL_SEL0, 3, 3) \
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DIV(K210_CLK_APB1, K210_SYSCTL_SEL0, 6, 3) \
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DIV(K210_CLK_APB2, K210_SYSCTL_SEL0, 9, 3) \
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DIV(K210_CLK_SRAM0, K210_SYSCTL_THR0, 0, 4) \
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DIV(K210_CLK_SRAM1, K210_SYSCTL_THR0, 4, 4) \
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DIV(K210_CLK_AI, K210_SYSCTL_THR0, 8, 4) \
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DIV(K210_CLK_DVP, K210_SYSCTL_THR0, 12, 4) \
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DIV(K210_CLK_ROM, K210_SYSCTL_THR0, 16, 4) \
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DIV(K210_CLK_SPI0, K210_SYSCTL_THR1, 0, 8) \
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DIV(K210_CLK_SPI1, K210_SYSCTL_THR1, 8, 8) \
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DIV(K210_CLK_SPI2, K210_SYSCTL_THR1, 16, 8) \
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DIV(K210_CLK_SPI3, K210_SYSCTL_THR1, 24, 8) \
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DIV(K210_CLK_TIMER0, K210_SYSCTL_THR2, 0, 8) \
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DIV(K210_CLK_TIMER1, K210_SYSCTL_THR2, 8, 8) \
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DIV(K210_CLK_TIMER2, K210_SYSCTL_THR2, 16, 8) \
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DIV(K210_CLK_I2S0, K210_SYSCTL_THR3, 0, 16) \
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DIV(K210_CLK_I2S1, K210_SYSCTL_THR3, 16, 16) \
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DIV(K210_CLK_I2S2, K210_SYSCTL_THR4, 0, 16) \
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DIV(K210_CLK_I2S0_M, K210_SYSCTL_THR4, 16, 8) \
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DIV(K210_CLK_I2S1_M, K210_SYSCTL_THR4, 24, 8) \
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DIV(K210_CLK_I2S2_M, K210_SYSCTL_THR4, 0, 8) \
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DIV(K210_CLK_I2C0, K210_SYSCTL_THR5, 8, 8) \
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DIV(K210_CLK_I2C1, K210_SYSCTL_THR5, 16, 8) \
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DIV(K210_CLK_I2C2, K210_SYSCTL_THR5, 24, 8) \
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DIV(K210_CLK_WDT0, K210_SYSCTL_THR6, 0, 8) \
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DIV(K210_CLK_WDT1, K210_SYSCTL_THR6, 8, 8)
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#define _DIVIFY(id) K210_CLK_DIV_##id
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#define DIVIFY(id) _DIVIFY(id)
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enum k210_div_ids {
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#define DIV_FLAGS(id, ...) DIVIFY(id),
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DIV_LIST
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#undef DIV_FLAGS
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};
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struct k210_div_params {
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u8 off;
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u8 shift;
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u8 width;
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u8 flags;
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};
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static const struct k210_div_params k210_divs[] = {
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#define DIV_FLAGS(id, _off, _shift, _width, _flags) \
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[DIVIFY(id)] = { \
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.off = (_off), \
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.shift = (_shift), \
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.width = (_width), \
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.flags = (_flags), \
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},
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DIV_LIST
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#undef DIV_FLAGS
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};
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#undef DIV
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#undef DIV_LIST
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#define GATE_LIST \
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GATE(K210_CLK_CPU, K210_SYSCTL_EN_CENT, 0) \
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GATE(K210_CLK_SRAM0, K210_SYSCTL_EN_CENT, 1) \
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GATE(K210_CLK_SRAM1, K210_SYSCTL_EN_CENT, 2) \
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GATE(K210_CLK_APB0, K210_SYSCTL_EN_CENT, 3) \
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GATE(K210_CLK_APB1, K210_SYSCTL_EN_CENT, 4) \
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GATE(K210_CLK_APB2, K210_SYSCTL_EN_CENT, 5) \
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GATE(K210_CLK_ROM, K210_SYSCTL_EN_PERI, 0) \
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GATE(K210_CLK_DMA, K210_SYSCTL_EN_PERI, 1) \
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GATE(K210_CLK_AI, K210_SYSCTL_EN_PERI, 2) \
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GATE(K210_CLK_DVP, K210_SYSCTL_EN_PERI, 3) \
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GATE(K210_CLK_FFT, K210_SYSCTL_EN_PERI, 4) \
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GATE(K210_CLK_GPIO, K210_SYSCTL_EN_PERI, 5) \
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GATE(K210_CLK_SPI0, K210_SYSCTL_EN_PERI, 6) \
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GATE(K210_CLK_SPI1, K210_SYSCTL_EN_PERI, 7) \
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GATE(K210_CLK_SPI2, K210_SYSCTL_EN_PERI, 8) \
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GATE(K210_CLK_SPI3, K210_SYSCTL_EN_PERI, 9) \
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GATE(K210_CLK_I2S0, K210_SYSCTL_EN_PERI, 10) \
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GATE(K210_CLK_I2S1, K210_SYSCTL_EN_PERI, 11) \
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GATE(K210_CLK_I2S2, K210_SYSCTL_EN_PERI, 12) \
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GATE(K210_CLK_I2C0, K210_SYSCTL_EN_PERI, 13) \
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GATE(K210_CLK_I2C1, K210_SYSCTL_EN_PERI, 14) \
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GATE(K210_CLK_I2C2, K210_SYSCTL_EN_PERI, 15) \
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GATE(K210_CLK_UART1, K210_SYSCTL_EN_PERI, 16) \
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GATE(K210_CLK_UART2, K210_SYSCTL_EN_PERI, 17) \
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GATE(K210_CLK_UART3, K210_SYSCTL_EN_PERI, 18) \
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GATE(K210_CLK_AES, K210_SYSCTL_EN_PERI, 19) \
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GATE(K210_CLK_FPIOA, K210_SYSCTL_EN_PERI, 20) \
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GATE(K210_CLK_TIMER0, K210_SYSCTL_EN_PERI, 21) \
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GATE(K210_CLK_TIMER1, K210_SYSCTL_EN_PERI, 22) \
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GATE(K210_CLK_TIMER2, K210_SYSCTL_EN_PERI, 23) \
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GATE(K210_CLK_WDT0, K210_SYSCTL_EN_PERI, 24) \
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GATE(K210_CLK_WDT1, K210_SYSCTL_EN_PERI, 25) \
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GATE(K210_CLK_SHA, K210_SYSCTL_EN_PERI, 26) \
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GATE(K210_CLK_OTP, K210_SYSCTL_EN_PERI, 27) \
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GATE(K210_CLK_RTC, K210_SYSCTL_EN_PERI, 29)
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#define _GATEIFY(id) K210_CLK_GATE_##id
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#define GATEIFY(id) _GATEIFY(id)
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enum k210_gate_ids {
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#define GATE(id, ...) GATEIFY(id),
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GATE_LIST
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#undef GATE
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};
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struct k210_gate_params {
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u8 off;
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u8 bit_idx;
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};
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static const struct k210_gate_params k210_gates[] = {
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#define GATE(id, _off, _idx) \
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[GATEIFY(id)] = { \
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.off = (_off), \
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.bit_idx = (_idx), \
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},
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GATE_LIST
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#undef GATE
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};
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#undef GATE_LIST
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#define MUX(id, reg, shift, width) \
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MUX_PARENTS(id, generic_sels, reg, shift, width)
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#define MUX_LIST \
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MUX_PARENTS(K210_CLK_PLL2, pll2_sels, K210_SYSCTL_PLL2, 26, 2) \
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MUX_PARENTS(K210_CLK_ACLK, aclk_sels, K210_SYSCTL_SEL0, 0, 1) \
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MUX(K210_CLK_SPI3, K210_SYSCTL_SEL0, 12, 1) \
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MUX(K210_CLK_TIMER0, K210_SYSCTL_SEL0, 13, 1) \
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MUX(K210_CLK_TIMER1, K210_SYSCTL_SEL0, 14, 1) \
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MUX(K210_CLK_TIMER2, K210_SYSCTL_SEL0, 15, 1)
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#define _MUXIFY(id) K210_CLK_MUX_##id
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#define MUXIFY(id) _MUXIFY(id)
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enum k210_mux_ids {
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#define MUX_PARENTS(id, ...) MUXIFY(id),
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MUX_LIST
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#undef MUX_PARENTS
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K210_CLK_MUX_NONE,
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};
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struct k210_mux_params {
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const char *const *parent_names;
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u8 num_parents;
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u8 off;
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u8 shift;
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u8 width;
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};
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static const struct k210_mux_params k210_muxes[] = {
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#define MUX_PARENTS(id, parents, _off, _shift, _width) \
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[MUXIFY(id)] = { \
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.parent_names = (const char * const *)(parents), \
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.num_parents = ARRAY_SIZE(parents), \
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.off = (_off), \
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.shift = (_shift), \
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.width = (_width), \
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},
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MUX_LIST
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#undef MUX_PARENTS
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};
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#undef MUX
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#undef MUX_LIST
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struct k210_pll_params {
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u8 off;
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u8 lock_off;
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u8 shift;
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u8 width;
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};
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static const struct k210_pll_params k210_plls[] = {
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#define PLL(_off, _shift, _width) { \
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.off = (_off), \
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.lock_off = K210_SYSCTL_PLL_LOCK, \
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.shift = (_shift), \
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.width = (_width), \
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}
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[0] = PLL(K210_SYSCTL_PLL0, 0, 2),
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[1] = PLL(K210_SYSCTL_PLL1, 8, 1),
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[2] = PLL(K210_SYSCTL_PLL2, 16, 1),
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#undef PLL
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};
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#define COMP(id) \
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COMP_FULL(id, MUXIFY(id), DIVIFY(id), GATEIFY(id))
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#define COMP_NOMUX(id) \
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COMP_FULL(id, K210_CLK_MUX_NONE, DIVIFY(id), GATEIFY(id))
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#define COMP_LIST \
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COMP(K210_CLK_SPI3) \
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COMP(K210_CLK_TIMER0) \
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COMP(K210_CLK_TIMER1) \
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COMP(K210_CLK_TIMER2) \
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COMP_NOMUX(K210_CLK_SRAM0) \
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COMP_NOMUX(K210_CLK_SRAM1) \
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COMP_NOMUX(K210_CLK_ROM) \
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COMP_NOMUX(K210_CLK_DVP) \
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COMP_NOMUX(K210_CLK_APB0) \
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COMP_NOMUX(K210_CLK_APB1) \
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COMP_NOMUX(K210_CLK_APB2) \
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COMP_NOMUX(K210_CLK_AI) \
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COMP_NOMUX(K210_CLK_I2S0) \
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COMP_NOMUX(K210_CLK_I2S1) \
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COMP_NOMUX(K210_CLK_I2S2) \
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COMP_NOMUX(K210_CLK_WDT0) \
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COMP_NOMUX(K210_CLK_WDT1) \
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COMP_NOMUX(K210_CLK_SPI0) \
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COMP_NOMUX(K210_CLK_SPI1) \
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COMP_NOMUX(K210_CLK_SPI2) \
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COMP_NOMUX(K210_CLK_I2C0) \
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COMP_NOMUX(K210_CLK_I2C1) \
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COMP_NOMUX(K210_CLK_I2C2)
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#define _COMPIFY(id) K210_CLK_COMP_##id
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#define COMPIFY(id) _COMPIFY(id)
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enum k210_comp_ids {
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#define COMP_FULL(id, ...) COMPIFY(id),
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COMP_LIST
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#undef COMP_FULL
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};
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struct k210_comp_params {
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u8 mux;
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u8 div;
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u8 gate;
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};
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static const struct k210_comp_params k210_comps[] = {
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#define COMP_FULL(id, _mux, _div, _gate) \
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[COMPIFY(id)] = { \
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.mux = (_mux), \
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.div = (_div), \
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.gate = (_gate), \
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},
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COMP_LIST
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#undef COMP_FULL
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};
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#undef COMP
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#undef COMP_ID
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#undef COMP_NOMUX
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#undef COMP_NOMUX_ID
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#undef COMP_LIST
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static struct clk *k210_bypass_children __section(".data");
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/* Helper functions to create sub-clocks */
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static struct clk_mux *k210_create_mux(const struct k210_mux_params *params,
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void *base)
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{
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struct clk_mux *mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return mux;
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mux->reg = base + params->off;
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mux->mask = BIT(params->width) - 1;
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mux->shift = params->shift;
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mux->parent_names = params->parent_names;
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mux->num_parents = params->num_parents;
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return mux;
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}
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static struct clk_divider *k210_create_div(const struct k210_div_params *params,
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void *base)
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{
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struct clk_divider *div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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return div;
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div->reg = base + params->off;
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div->shift = params->shift;
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div->width = params->width;
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div->flags = params->flags;
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return div;
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}
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static struct clk_gate *k210_create_gate(const struct k210_gate_params *params,
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void *base)
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{
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struct clk_gate *gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return gate;
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gate->reg = base + params->off;
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gate->bit_idx = params->bit_idx;
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return gate;
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}
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static struct k210_pll *k210_create_pll(const struct k210_pll_params *params,
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void *base)
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{
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struct k210_pll *pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return pll;
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pll->reg = base + params->off;
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pll->lock = base + params->lock_off;
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pll->shift = params->shift;
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pll->width = params->width;
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return pll;
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}
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/* Create all sub-clocks, and then register the composite clock */
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static struct clk *k210_register_comp(const struct k210_comp_params *params,
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void *base, const char *name,
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const char *parent)
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{
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const char *const *parent_names;
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int num_parents;
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struct clk *comp;
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const struct clk_ops *mux_ops;
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struct clk_mux *mux;
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struct clk_divider *div;
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struct clk_gate *gate;
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if (params->mux == K210_CLK_MUX_NONE) {
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if (!parent)
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return ERR_PTR(-EINVAL);
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mux_ops = NULL;
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mux = NULL;
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parent_names = &parent;
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num_parents = 1;
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} else {
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mux_ops = &clk_mux_ops;
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mux = k210_create_mux(&k210_muxes[params->mux], base);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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parent_names = mux->parent_names;
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num_parents = mux->num_parents;
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}
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div = k210_create_div(&k210_divs[params->div], base);
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if (!div) {
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comp = ERR_PTR(-ENOMEM);
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goto cleanup_mux;
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}
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gate = k210_create_gate(&k210_gates[params->gate], base);
|
|
if (!gate) {
|
|
comp = ERR_PTR(-ENOMEM);
|
|
goto cleanup_div;
|
|
}
|
|
|
|
comp = clk_register_composite(NULL, name, parent_names, num_parents,
|
|
&mux->clk, mux_ops,
|
|
&div->clk, &clk_divider_ops,
|
|
&gate->clk, &clk_gate_ops, 0);
|
|
if (IS_ERR(comp))
|
|
goto cleanup_gate;
|
|
return comp;
|
|
|
|
cleanup_gate:
|
|
free(gate);
|
|
cleanup_div:
|
|
free(div);
|
|
cleanup_mux:
|
|
free(mux);
|
|
return comp;
|
|
}
|
|
|
|
static bool __section(".data") probed;
|
|
|
|
/* reset probed so we will probe again post-relocation */
|
|
static int k210_clk_bind(struct udevice *dev)
|
|
{
|
|
probed = false;
|
|
return 0;
|
|
}
|
|
|
|
static int k210_clk_probe(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
const char *in0;
|
|
struct clk *in0_clk, *bypass;
|
|
struct clk_mux *mux;
|
|
struct clk_divider *div;
|
|
struct k210_pll *pll;
|
|
void *base;
|
|
|
|
/*
|
|
* Only one instance of this driver allowed. This prevents weird bugs
|
|
* when the driver fails part-way through probing. Some clocks will
|
|
* already have been registered, and re-probing will register them
|
|
* again, creating a bunch of duplicates. Better error-handling/cleanup
|
|
* could fix this, but it's Probably Not Worth It (TM).
|
|
*/
|
|
if (probed)
|
|
return -EINVAL;
|
|
|
|
base = dev_read_addr_ptr(dev_get_parent(dev));
|
|
if (!base)
|
|
return -EINVAL;
|
|
|
|
in0_clk = kzalloc(sizeof(*in0_clk), GFP_KERNEL);
|
|
if (!in0_clk)
|
|
return -ENOMEM;
|
|
|
|
ret = clk_get_by_index(dev, 0, in0_clk);
|
|
if (ret)
|
|
return ret;
|
|
in0 = in0_clk->dev->name;
|
|
|
|
probed = true;
|
|
|
|
aclk_sels[0] = in0;
|
|
pll2_sels[0] = in0;
|
|
|
|
/*
|
|
* All PLLs have a broken bypass, but pll0 has the CPU downstream, so we
|
|
* need to manually reparent it whenever we configure pll0
|
|
*/
|
|
pll = k210_create_pll(&k210_plls[0], base);
|
|
if (pll) {
|
|
bypass = k210_register_bypass("pll0", in0, &pll->clk,
|
|
&k210_pll_ops, in0_clk);
|
|
clk_dm(K210_CLK_PLL0, bypass);
|
|
} else {
|
|
return -ENOMEM;
|
|
}
|
|
|
|
pll = k210_create_pll(&k210_plls[1], base);
|
|
if (pll)
|
|
clk_dm(K210_CLK_PLL1,
|
|
k210_register_pll_struct("pll1", in0, pll));
|
|
|
|
/* PLL2 is muxed, so set up a composite clock */
|
|
mux = k210_create_mux(&k210_muxes[MUXIFY(K210_CLK_PLL2)], base);
|
|
pll = k210_create_pll(&k210_plls[2], base);
|
|
if (!mux || !pll) {
|
|
free(mux);
|
|
free(pll);
|
|
} else {
|
|
clk_dm(K210_CLK_PLL2,
|
|
clk_register_composite(NULL, "pll2", pll2_sels,
|
|
ARRAY_SIZE(pll2_sels),
|
|
&mux->clk, &clk_mux_ops,
|
|
&pll->clk, &k210_pll_ops,
|
|
&pll->clk, &k210_pll_ops, 0));
|
|
}
|
|
|
|
/* Half-frequency clocks for "even" dividers */
|
|
clk_dm(K210_CLK_IN0_H, k210_clk_half("in0_half", in0));
|
|
clk_dm(K210_CLK_PLL0_H, k210_clk_half("pll0_half", "pll0"));
|
|
clk_dm(K210_CLK_PLL2_H, k210_clk_half("pll2_half", "pll2"));
|
|
|
|
/* ACLK has no gate */
|
|
mux = k210_create_mux(&k210_muxes[MUXIFY(K210_CLK_ACLK)], base);
|
|
div = k210_create_div(&k210_divs[DIVIFY(K210_CLK_ACLK)], base);
|
|
if (!mux || !div) {
|
|
free(mux);
|
|
free(div);
|
|
} else {
|
|
struct clk *aclk =
|
|
clk_register_composite(NULL, "aclk", aclk_sels,
|
|
ARRAY_SIZE(aclk_sels),
|
|
&mux->clk, &clk_mux_ops,
|
|
&div->clk, &clk_divider_ops,
|
|
NULL, NULL, 0);
|
|
clk_dm(K210_CLK_ACLK, aclk);
|
|
if (!IS_ERR(aclk)) {
|
|
k210_bypass_children = aclk;
|
|
k210_bypass_set_children(bypass,
|
|
&k210_bypass_children, 1);
|
|
}
|
|
}
|
|
|
|
#define REGISTER_COMP(id, name) \
|
|
clk_dm(id, \
|
|
k210_register_comp(&k210_comps[COMPIFY(id)], base, name, NULL))
|
|
REGISTER_COMP(K210_CLK_SPI3, "spi3");
|
|
REGISTER_COMP(K210_CLK_TIMER0, "timer0");
|
|
REGISTER_COMP(K210_CLK_TIMER1, "timer1");
|
|
REGISTER_COMP(K210_CLK_TIMER2, "timer2");
|
|
#undef REGISTER_COMP
|
|
|
|
/* Dividing clocks, no mux */
|
|
#define REGISTER_COMP_NOMUX(id, name, parent) \
|
|
clk_dm(id, \
|
|
k210_register_comp(&k210_comps[COMPIFY(id)], base, name, parent))
|
|
REGISTER_COMP_NOMUX(K210_CLK_SRAM0, "sram0", "aclk");
|
|
REGISTER_COMP_NOMUX(K210_CLK_SRAM1, "sram1", "aclk");
|
|
REGISTER_COMP_NOMUX(K210_CLK_ROM, "rom", "aclk");
|
|
REGISTER_COMP_NOMUX(K210_CLK_DVP, "dvp", "aclk");
|
|
REGISTER_COMP_NOMUX(K210_CLK_APB0, "apb0", "aclk");
|
|
REGISTER_COMP_NOMUX(K210_CLK_APB1, "apb1", "aclk");
|
|
REGISTER_COMP_NOMUX(K210_CLK_APB2, "apb2", "aclk");
|
|
REGISTER_COMP_NOMUX(K210_CLK_AI, "ai", "pll1");
|
|
REGISTER_COMP_NOMUX(K210_CLK_I2S0, "i2s0", "pll2_half");
|
|
REGISTER_COMP_NOMUX(K210_CLK_I2S1, "i2s1", "pll2_half");
|
|
REGISTER_COMP_NOMUX(K210_CLK_I2S2, "i2s2", "pll2_half");
|
|
REGISTER_COMP_NOMUX(K210_CLK_WDT0, "wdt0", "in0_half");
|
|
REGISTER_COMP_NOMUX(K210_CLK_WDT1, "wdt1", "in0_half");
|
|
REGISTER_COMP_NOMUX(K210_CLK_SPI0, "spi0", "pll0_half");
|
|
REGISTER_COMP_NOMUX(K210_CLK_SPI1, "spi1", "pll0_half");
|
|
REGISTER_COMP_NOMUX(K210_CLK_SPI2, "spi2", "pll0_half");
|
|
REGISTER_COMP_NOMUX(K210_CLK_I2C0, "i2c0", "pll0_half");
|
|
REGISTER_COMP_NOMUX(K210_CLK_I2C1, "i2c1", "pll0_half");
|
|
REGISTER_COMP_NOMUX(K210_CLK_I2C2, "i2c2", "pll0_half");
|
|
#undef REGISTER_COMP_NOMUX
|
|
|
|
/* Dividing clocks */
|
|
#define REGISTER_DIV(id, name, parent) do {\
|
|
const struct k210_div_params *params = &k210_divs[DIVIFY(id)]; \
|
|
clk_dm(id, \
|
|
clk_register_divider(NULL, name, parent, 0, base + params->off, \
|
|
params->shift, params->width, 0)); \
|
|
} while (false)
|
|
REGISTER_DIV(K210_CLK_I2S0_M, "i2s0_m", "pll2_half");
|
|
REGISTER_DIV(K210_CLK_I2S1_M, "i2s1_m", "pll2_half");
|
|
REGISTER_DIV(K210_CLK_I2S2_M, "i2s2_m", "pll2_half");
|
|
#undef REGISTER_DIV
|
|
|
|
/* Gated clocks */
|
|
#define REGISTER_GATE(id, name, parent) do { \
|
|
const struct k210_gate_params *params = &k210_gates[GATEIFY(id)]; \
|
|
clk_dm(id, \
|
|
clk_register_gate(NULL, name, parent, 0, base + params->off, \
|
|
params->bit_idx, 0, NULL)); \
|
|
} while (false)
|
|
REGISTER_GATE(K210_CLK_CPU, "cpu", "aclk");
|
|
REGISTER_GATE(K210_CLK_DMA, "dma", "aclk");
|
|
REGISTER_GATE(K210_CLK_FFT, "fft", "aclk");
|
|
REGISTER_GATE(K210_CLK_GPIO, "gpio", "apb0");
|
|
REGISTER_GATE(K210_CLK_UART1, "uart1", "apb0");
|
|
REGISTER_GATE(K210_CLK_UART2, "uart2", "apb0");
|
|
REGISTER_GATE(K210_CLK_UART3, "uart3", "apb0");
|
|
REGISTER_GATE(K210_CLK_FPIOA, "fpioa", "apb0");
|
|
REGISTER_GATE(K210_CLK_SHA, "sha", "apb0");
|
|
REGISTER_GATE(K210_CLK_AES, "aes", "apb1");
|
|
REGISTER_GATE(K210_CLK_OTP, "otp", "apb1");
|
|
REGISTER_GATE(K210_CLK_RTC, "rtc", in0);
|
|
#undef REGISTER_GATE
|
|
|
|
/* The MTIME register in CLINT runs at one 50th the CPU clock speed */
|
|
clk_dm(K210_CLK_CLINT,
|
|
clk_register_fixed_factor(NULL, "clint", "aclk", 0, 1, 50));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id k210_clk_ids[] = {
|
|
{ .compatible = "kendryte,k210-clk" },
|
|
{ },
|
|
};
|
|
|
|
U_BOOT_DRIVER(k210_clk) = {
|
|
.name = "k210_clk",
|
|
.id = UCLASS_CLK,
|
|
.of_match = k210_clk_ids,
|
|
.ops = &k210_clk_ops,
|
|
.bind = k210_clk_bind,
|
|
.probe = k210_clk_probe,
|
|
};
|