mirror of
https://github.com/brain-hackers/u-boot-brain
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![York Sun](/assets/img/avatar_default.png)
U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: York Sun <yorksun@freescale.com>
657 lines
15 KiB
C
657 lines
15 KiB
C
/*
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* Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
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* (C) Copyright 2002, 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <fsl_esdhc.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <fsl_ifc.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_lbc.h>
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#include <post.h>
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#include <asm/processor.h>
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#include <fsl_ddr_sdram.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Default board reset function
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*/
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static void
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__board_reset(void)
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{
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/* Do nothing */
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}
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void board_reset(void) __attribute__((weak, alias("__board_reset")));
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int checkcpu (void)
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{
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sys_info_t sysinfo;
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uint pvr, svr;
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uint ver;
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uint major, minor;
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struct cpu_type *cpu;
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char buf1[32], buf2[32];
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#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
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ccsr_gur_t __iomem *gur =
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(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#endif
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/*
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* Cornet platforms use ddr sync bit in RCW to indicate sync vs async
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* mode. Previous platform use ddr ratio to do the same. This
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* information is only for display here.
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*/
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#ifdef CONFIG_FSL_CORENET
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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u32 ddr_sync = 0; /* only async mode is supported */
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#else
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u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
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>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
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#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
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#else /* CONFIG_FSL_CORENET */
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#ifdef CONFIG_DDR_CLK_FREQ
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u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
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>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
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#else
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u32 ddr_ratio = 0;
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#endif /* CONFIG_DDR_CLK_FREQ */
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#endif /* CONFIG_FSL_CORENET */
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unsigned int i, core, nr_cores = cpu_numcores();
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u32 mask = cpu_mask();
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svr = get_svr();
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major = SVR_MAJ(svr);
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minor = SVR_MIN(svr);
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#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
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if (SVR_SOC_VER(svr) == SVR_T4080) {
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ccsr_rcpm_t *rcpm =
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(void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
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setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
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FSL_CORENET_DEVDISR2_DTSEC1_9);
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setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
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setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
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/* It needs SW to disable core4~7 as HW design sake on T4080 */
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for (i = 4; i < 8; i++)
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cpu_disable(i);
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/* request core4~7 into PH20 state, prior to entering PCL10
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* state, all cores in cluster should be placed in PH20 state.
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*/
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setbits_be32(&rcpm->pcph20setr, 0xf0);
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/* put the 2nd cluster into PCL10 state */
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setbits_be32(&rcpm->clpcl10setr, 1 << 1);
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}
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#endif
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if (cpu_numcores() > 1) {
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#ifndef CONFIG_MP
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puts("Unicore software on multiprocessor system!!\n"
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"To enable mutlticore build define CONFIG_MP\n");
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#endif
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volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
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printf("CPU%d: ", pic->whoami);
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} else {
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puts("CPU: ");
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}
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cpu = gd->arch.cpu;
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puts(cpu->name);
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if (IS_E_PROCESSOR(svr))
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puts("E");
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
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pvr = get_pvr();
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ver = PVR_VER(pvr);
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major = PVR_MAJ(pvr);
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minor = PVR_MIN(pvr);
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printf("Core: ");
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switch(ver) {
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case PVR_VER_E500_V1:
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case PVR_VER_E500_V2:
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puts("e500");
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break;
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case PVR_VER_E500MC:
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puts("e500mc");
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break;
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case PVR_VER_E5500:
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puts("e5500");
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break;
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case PVR_VER_E6500:
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puts("e6500");
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break;
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default:
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puts("Unknown");
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break;
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}
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
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if (nr_cores > CONFIG_MAX_CPUS) {
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panic("\nUnexpected number of cores: %d, max is %d\n",
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nr_cores, CONFIG_MAX_CPUS);
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}
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get_sys_info(&sysinfo);
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#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
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if (sysinfo.diff_sysclk == 1)
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puts("Single Source Clock Configuration\n");
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#endif
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puts("Clock Configuration:");
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for_each_cpu(i, core, nr_cores, mask) {
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if (!(i & 3))
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printf ("\n ");
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printf("CPU%d:%-4s MHz, ", core,
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strmhz(buf1, sysinfo.freq_processor[core]));
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}
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printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
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printf("\n");
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#ifdef CONFIG_FSL_CORENET
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if (ddr_sync == 1) {
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printf(" DDR:%-4s MHz (%s MT/s data rate) "
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"(Synchronous), ",
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strmhz(buf1, sysinfo.freq_ddrbus/2),
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strmhz(buf2, sysinfo.freq_ddrbus));
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} else {
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printf(" DDR:%-4s MHz (%s MT/s data rate) "
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"(Asynchronous), ",
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strmhz(buf1, sysinfo.freq_ddrbus/2),
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strmhz(buf2, sysinfo.freq_ddrbus));
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}
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#else
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switch (ddr_ratio) {
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case 0x0:
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printf(" DDR:%-4s MHz (%s MT/s data rate), ",
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strmhz(buf1, sysinfo.freq_ddrbus/2),
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strmhz(buf2, sysinfo.freq_ddrbus));
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break;
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case 0x7:
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printf(" DDR:%-4s MHz (%s MT/s data rate) "
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"(Synchronous), ",
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strmhz(buf1, sysinfo.freq_ddrbus/2),
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strmhz(buf2, sysinfo.freq_ddrbus));
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break;
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default:
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printf(" DDR:%-4s MHz (%s MT/s data rate) "
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"(Asynchronous), ",
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strmhz(buf1, sysinfo.freq_ddrbus/2),
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strmhz(buf2, sysinfo.freq_ddrbus));
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break;
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}
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#endif
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#if defined(CONFIG_FSL_LBC)
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if (sysinfo.freq_localbus > LCRR_CLKDIV) {
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printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
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} else {
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printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
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sysinfo.freq_localbus);
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}
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#endif
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#if defined(CONFIG_FSL_IFC)
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printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
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#endif
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#ifdef CONFIG_CPM2
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printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
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#endif
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#ifdef CONFIG_QE
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printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
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printf(" FMAN%d: %s MHz\n", i + 1,
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strmhz(buf1, sysinfo.freq_fman[i]));
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}
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#endif
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#ifdef CONFIG_SYS_DPAA_QBMAN
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printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
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#endif
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#ifdef CONFIG_SYS_DPAA_PME
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printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
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#endif
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puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
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#ifdef CONFIG_FSL_CORENET
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/* Display the RCW, so that no one gets confused as to what RCW
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* we're actually using for this boot.
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*/
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puts("Reset Configuration Word (RCW):");
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for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
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u32 rcw = in_be32(&gur->rcwsr[i]);
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if ((i % 4) == 0)
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printf("\n %08x:", i * 4);
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printf(" %08x", rcw);
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}
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puts("\n");
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#endif
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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/* Everything after the first generation of PQ3 parts has RSTCR */
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#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
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defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
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unsigned long val, msr;
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/*
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* Initiate hard reset in debug control register DBCR0
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* Make sure MSR[DE] = 1. This only resets the core.
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*/
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msr = mfmsr ();
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msr |= MSR_DE;
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mtmsr (msr);
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val = mfspr(DBCR0);
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val |= 0x70000000;
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mtspr(DBCR0,val);
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#else
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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/* Attempt board-specific reset */
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board_reset();
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/* Next try asserting HRESET_REQ */
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out_be32(&gur->rstcr, 0x2);
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udelay(100);
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#endif
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return 1;
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}
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/*
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* Get timebase clock frequency
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*/
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#ifndef CONFIG_SYS_FSL_TBCLK_DIV
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#define CONFIG_SYS_FSL_TBCLK_DIV 8
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#endif
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__weak unsigned long get_tbclk (void)
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{
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unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
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return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
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}
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#if defined(CONFIG_WATCHDOG)
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#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
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void
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init_85xx_watchdog(void)
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{
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mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
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TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
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}
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void
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reset_85xx_watchdog(void)
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{
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/*
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* Clear TSR(WIS) bit by writing 1
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*/
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mtspr(SPRN_TSR, TSR_WIS);
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}
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void
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watchdog_reset(void)
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{
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int re_enable = disable_interrupts();
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reset_85xx_watchdog();
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if (re_enable)
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enable_interrupts();
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}
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#endif /* CONFIG_WATCHDOG */
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/*
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* Initializes on-chip MMC controllers.
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* to override, implement board_mmc_init()
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*/
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int cpu_mmc_init(bd_t *bis)
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{
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#ifdef CONFIG_FSL_ESDHC
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return fsl_esdhc_mmc_init(bis);
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#else
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return 0;
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#endif
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}
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/*
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* Print out the state of various machine registers.
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* Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
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* parameters for IFC and TLBs
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*/
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void mpc85xx_reginfo(void)
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{
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print_tlbcam();
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print_laws();
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#if defined(CONFIG_FSL_LBC)
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print_lbc_regs();
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#endif
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#ifdef CONFIG_FSL_IFC
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print_ifc_regs();
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#endif
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}
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/* Common ddr init for non-corenet fsl 85xx platforms */
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#ifndef CONFIG_FSL_CORENET
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#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
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!defined(CONFIG_SYS_INIT_L2_ADDR)
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phys_size_t initdram(int board_type)
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{
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#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
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defined(CONFIG_QEMU_E500)
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return fsl_ddr_sdram_size();
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#else
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return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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#endif
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}
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#else /* CONFIG_SYS_RAMBOOT */
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size = 0;
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#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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unsigned int x = 10;
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unsigned int i;
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/*
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* Work around to stabilize DDR DLL
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*/
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out_be32(&gur->ddrdllcr, 0x81000000);
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asm("sync;isync;msync");
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udelay(200);
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while (in_be32(&gur->ddrdllcr) != 0x81000100) {
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setbits_be32(&gur->devdisr, 0x00010000);
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for (i = 0; i < x; i++)
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;
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clrbits_be32(&gur->devdisr, 0x00010000);
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x++;
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}
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}
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#endif
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#if defined(CONFIG_SPD_EEPROM) || \
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defined(CONFIG_DDR_SPD) || \
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defined(CONFIG_SYS_DDR_RAW_TIMING)
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dram_size = fsl_ddr_sdram();
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#else
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dram_size = fixed_sdram();
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#endif
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(dram_size);
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#endif
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#if defined(CONFIG_FSL_LBC)
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/* Some boards also have sdram on the lbc */
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lbc_sdram_init();
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#endif
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debug("DDR: ");
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return dram_size;
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}
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#endif /* CONFIG_SYS_RAMBOOT */
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#endif
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#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
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/* Board-specific functions defined in each board's ddr.c */
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void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
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unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
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void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
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phys_addr_t *rpn);
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unsigned int
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setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
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void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
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static void dump_spd_ddr_reg(void)
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{
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int i, j, k, m;
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u8 *p_8;
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u32 *p_32;
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struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
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generic_spd_eeprom_t
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spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
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fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
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puts("SPD data of all dimms (zero vaule is omitted)...\n");
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puts("Byte (hex) ");
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k = 1;
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
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printf("Dimm%d ", k++);
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}
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puts("\n");
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for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
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m = 0;
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printf("%3d (0x%02x) ", k, k);
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
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p_8 = (u8 *) &spd[i][j];
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if (p_8[k]) {
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printf("0x%02x ", p_8[k]);
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m++;
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} else
|
|
puts(" ");
|
|
}
|
|
}
|
|
if (m)
|
|
puts("\n");
|
|
else
|
|
puts("\r");
|
|
}
|
|
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
|
switch (i) {
|
|
case 0:
|
|
ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
|
break;
|
|
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
|
|
case 1:
|
|
ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
|
|
break;
|
|
#endif
|
|
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
|
|
case 2:
|
|
ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
|
|
break;
|
|
#endif
|
|
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
|
|
case 3:
|
|
ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
|
|
break;
|
|
#endif
|
|
default:
|
|
printf("%s unexpected controller number = %u\n",
|
|
__func__, i);
|
|
return;
|
|
}
|
|
}
|
|
printf("DDR registers dump for all controllers "
|
|
"(zero vaule is omitted)...\n");
|
|
puts("Offset (hex) ");
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
|
|
printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
|
|
puts("\n");
|
|
for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
|
|
m = 0;
|
|
printf("%6d (0x%04x)", k * 4, k * 4);
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
|
p_32 = (u32 *) ddr[i];
|
|
if (p_32[k]) {
|
|
printf(" 0x%08x", p_32[k]);
|
|
m++;
|
|
} else
|
|
puts(" ");
|
|
}
|
|
if (m)
|
|
puts("\n");
|
|
else
|
|
puts("\r");
|
|
}
|
|
puts("\n");
|
|
}
|
|
|
|
/* invalid the TLBs for DDR and setup new ones to cover p_addr */
|
|
static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
|
|
{
|
|
u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
|
|
unsigned long epn;
|
|
u32 tsize, valid, ptr;
|
|
int ddr_esel;
|
|
|
|
clear_ddr_tlbs_phys(p_addr, size>>20);
|
|
|
|
/* Setup new tlb to cover the physical address */
|
|
setup_ddr_tlbs_phys(p_addr, size>>20);
|
|
|
|
ptr = vstart;
|
|
ddr_esel = find_tlb_idx((void *)ptr, 1);
|
|
if (ddr_esel != -1) {
|
|
read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
|
|
} else {
|
|
printf("TLB error in function %s\n", __func__);
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* slide the testing window up to test another area
|
|
* for 32_bit system, the maximum testable memory is limited to
|
|
* CONFIG_MAX_MEM_MAPPED
|
|
*/
|
|
int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
|
|
{
|
|
phys_addr_t test_cap, p_addr;
|
|
phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
|
|
|
|
#if !defined(CONFIG_PHYS_64BIT) || \
|
|
!defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
|
|
(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
|
|
test_cap = p_size;
|
|
#else
|
|
test_cap = gd->ram_size;
|
|
#endif
|
|
p_addr = (*vstart) + (*size) + (*phys_offset);
|
|
if (p_addr < test_cap - 1) {
|
|
p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
|
|
if (reset_tlb(p_addr, p_size, phys_offset) == -1)
|
|
return -1;
|
|
*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
|
|
*size = (u32) p_size;
|
|
printf("Testing 0x%08llx - 0x%08llx\n",
|
|
(u64)(*vstart) + (*phys_offset),
|
|
(u64)(*vstart) + (*phys_offset) + (*size) - 1);
|
|
} else
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* initialization for testing area */
|
|
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
|
|
{
|
|
phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
|
|
|
|
*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
|
|
*size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
|
|
*phys_offset = 0;
|
|
|
|
#if !defined(CONFIG_PHYS_64BIT) || \
|
|
!defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
|
|
(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
|
|
if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
|
|
puts("Cannot test more than ");
|
|
print_size(CONFIG_MAX_MEM_MAPPED,
|
|
" without proper 36BIT support.\n");
|
|
}
|
|
#endif
|
|
printf("Testing 0x%08llx - 0x%08llx\n",
|
|
(u64)(*vstart) + (*phys_offset),
|
|
(u64)(*vstart) + (*phys_offset) + (*size) - 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* invalid TLBs for DDR and remap as normal after testing */
|
|
int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
|
|
{
|
|
unsigned long epn;
|
|
u32 tsize, valid, ptr;
|
|
phys_addr_t rpn = 0;
|
|
int ddr_esel;
|
|
|
|
/* disable the TLBs for this testing */
|
|
ptr = *vstart;
|
|
|
|
while (ptr < (*vstart) + (*size)) {
|
|
ddr_esel = find_tlb_idx((void *)ptr, 1);
|
|
if (ddr_esel != -1) {
|
|
read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
|
|
disable_tlb(ddr_esel);
|
|
}
|
|
ptr += TSIZE_TO_BYTES(tsize);
|
|
}
|
|
|
|
puts("Remap DDR ");
|
|
setup_ddr_tlbs(gd->ram_size>>20);
|
|
puts("\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
void arch_memory_failure_handle(void)
|
|
{
|
|
dump_spd_ddr_reg();
|
|
}
|
|
#endif
|