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https://github.com/brain-hackers/u-boot-brain
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d60a2099a2
The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
42 lines
980 B
C
42 lines
980 B
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/immap_ls102xa.h>
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static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
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[0x00] = {PCIE1, PCIE1, PCIE1, PCIE1},
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[0x10] = {PCIE1, SATA1, PCIE2, PCIE2},
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[0x20] = {PCIE1, SGMII_TSEC1, PCIE2, SGMII_TSEC2},
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[0x30] = {PCIE1, SATA1, SGMII_TSEC1, SGMII_TSEC2},
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[0x40] = {PCIE1, PCIE1, SATA1, SGMII_TSEC2},
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[0x50] = {PCIE1, PCIE1, PCIE2, SGMII_TSEC2},
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[0x60] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
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[0x70] = {PCIE1, SATA1, PCIE2, SGMII_TSEC2},
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[0x80] = {PCIE2, PCIE2, PCIE2, PCIE2},
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};
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
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{
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return serdes_cfg_tbl[cfg][lane];
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}
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int is_serdes_prtcl_valid(int serdes, u32 prtcl)
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{
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int i;
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if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (serdes_cfg_tbl[prtcl][i] != NONE)
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return 1;
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}
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return 0;
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}
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