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https://github.com/brain-hackers/u-boot-brain
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![Álvaro Fernández Rojas](/assets/img/avatar_default.png)
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
538 lines
13 KiB
C
538 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c:
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dma.h>
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#include <miiphy.h>
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#include <net.h>
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#include <phy.h>
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#include <reset.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#define ETH_RX_DESC PKTBUFSRX
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#define ETH_MAX_MTU_SIZE 1518
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#define ETH_TIMEOUT 100
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#define ETH_TX_WATERMARK 32
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/* ETH Receiver Configuration register */
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#define ETH_RXCFG_REG 0x00
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#define ETH_RXCFG_ENFLOW_SHIFT 5
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#define ETH_RXCFG_ENFLOW_MASK (1 << ETH_RXCFG_ENFLOW_SHIFT)
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/* ETH Receive Maximum Length register */
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#define ETH_RXMAXLEN_REG 0x04
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#define ETH_RXMAXLEN_SHIFT 0
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#define ETH_RXMAXLEN_MASK (0x7ff << ETH_RXMAXLEN_SHIFT)
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/* ETH Transmit Maximum Length register */
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#define ETH_TXMAXLEN_REG 0x08
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#define ETH_TXMAXLEN_SHIFT 0
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#define ETH_TXMAXLEN_MASK (0x7ff << ETH_TXMAXLEN_SHIFT)
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/* MII Status/Control register */
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#define MII_SC_REG 0x10
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#define MII_SC_MDCFREQDIV_SHIFT 0
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#define MII_SC_MDCFREQDIV_MASK (0x7f << MII_SC_MDCFREQDIV_SHIFT)
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#define MII_SC_PREAMBLE_EN_SHIFT 7
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#define MII_SC_PREAMBLE_EN_MASK (1 << MII_SC_PREAMBLE_EN_SHIFT)
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/* MII Data register */
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#define MII_DAT_REG 0x14
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#define MII_DAT_DATA_SHIFT 0
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#define MII_DAT_DATA_MASK (0xffff << MII_DAT_DATA_SHIFT)
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#define MII_DAT_TA_SHIFT 16
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#define MII_DAT_TA_MASK (0x3 << MII_DAT_TA_SHIFT)
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#define MII_DAT_REG_SHIFT 18
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#define MII_DAT_REG_MASK (0x1f << MII_DAT_REG_SHIFT)
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#define MII_DAT_PHY_SHIFT 23
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#define MII_DAT_PHY_MASK (0x1f << MII_DAT_PHY_SHIFT)
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#define MII_DAT_OP_SHIFT 28
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#define MII_DAT_OP_WRITE (0x5 << MII_DAT_OP_SHIFT)
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#define MII_DAT_OP_READ (0x6 << MII_DAT_OP_SHIFT)
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/* ETH Interrupts Mask register */
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#define ETH_IRMASK_REG 0x18
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/* ETH Interrupts register */
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#define ETH_IR_REG 0x1c
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#define ETH_IR_MII_SHIFT 0
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#define ETH_IR_MII_MASK (1 << ETH_IR_MII_SHIFT)
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/* ETH Control register */
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#define ETH_CTL_REG 0x2c
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#define ETH_CTL_ENABLE_SHIFT 0
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#define ETH_CTL_ENABLE_MASK (1 << ETH_CTL_ENABLE_SHIFT)
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#define ETH_CTL_DISABLE_SHIFT 1
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#define ETH_CTL_DISABLE_MASK (1 << ETH_CTL_DISABLE_SHIFT)
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#define ETH_CTL_RESET_SHIFT 2
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#define ETH_CTL_RESET_MASK (1 << ETH_CTL_RESET_SHIFT)
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#define ETH_CTL_EPHY_SHIFT 3
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#define ETH_CTL_EPHY_MASK (1 << ETH_CTL_EPHY_SHIFT)
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/* ETH Transmit Control register */
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#define ETH_TXCTL_REG 0x30
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#define ETH_TXCTL_FD_SHIFT 0
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#define ETH_TXCTL_FD_MASK (1 << ETH_TXCTL_FD_SHIFT)
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/* ETH Transmit Watermask register */
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#define ETH_TXWMARK_REG 0x34
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#define ETH_TXWMARK_WM_SHIFT 0
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#define ETH_TXWMARK_WM_MASK (0x3f << ETH_TXWMARK_WM_SHIFT)
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/* MIB Control register */
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#define MIB_CTL_REG 0x38
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#define MIB_CTL_RDCLEAR_SHIFT 0
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#define MIB_CTL_RDCLEAR_MASK (1 << MIB_CTL_RDCLEAR_SHIFT)
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/* ETH Perfect Match registers */
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#define ETH_PM_CNT 4
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#define ETH_PML_REG(x) (0x58 + (x) * 0x8)
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#define ETH_PMH_REG(x) (0x5c + (x) * 0x8)
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#define ETH_PMH_VALID_SHIFT 16
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#define ETH_PMH_VALID_MASK (1 << ETH_PMH_VALID_SHIFT)
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/* MIB Counters registers */
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#define MIB_REG_CNT 55
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#define MIB_REG(x) (0x200 + (x) * 4)
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/* ETH data */
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struct bcm6348_eth_priv {
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void __iomem *base;
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/* DMA */
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struct dma rx_dma;
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struct dma tx_dma;
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/* PHY */
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int phy_id;
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struct phy_device *phy_dev;
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};
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static void bcm6348_eth_mac_disable(struct bcm6348_eth_priv *priv)
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{
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/* disable emac */
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clrsetbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_ENABLE_MASK,
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ETH_CTL_DISABLE_MASK);
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/* wait until emac is disabled */
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if (wait_for_bit_be32(priv->base + ETH_CTL_REG,
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ETH_CTL_DISABLE_MASK, false,
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ETH_TIMEOUT, false))
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pr_err("%s: error disabling emac\n", __func__);
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}
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static void bcm6348_eth_mac_enable(struct bcm6348_eth_priv *priv)
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{
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setbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_ENABLE_MASK);
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}
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static void bcm6348_eth_mac_reset(struct bcm6348_eth_priv *priv)
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{
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/* reset emac */
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writel_be(ETH_CTL_RESET_MASK, priv->base + ETH_CTL_REG);
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wmb();
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/* wait until emac is reset */
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if (wait_for_bit_be32(priv->base + ETH_CTL_REG,
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ETH_CTL_RESET_MASK, false,
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ETH_TIMEOUT, false))
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pr_err("%s: error resetting emac\n", __func__);
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}
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static int bcm6348_eth_free_pkt(struct udevice *dev, uchar *packet, int len)
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{
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struct bcm6348_eth_priv *priv = dev_get_priv(dev);
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return dma_prepare_rcv_buf(&priv->rx_dma, packet, len);
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}
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static int bcm6348_eth_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct bcm6348_eth_priv *priv = dev_get_priv(dev);
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return dma_receive(&priv->rx_dma, (void**)packetp, NULL);
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}
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static int bcm6348_eth_send(struct udevice *dev, void *packet, int length)
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{
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struct bcm6348_eth_priv *priv = dev_get_priv(dev);
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return dma_send(&priv->tx_dma, packet, length, NULL);
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}
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static int bcm6348_eth_adjust_link(struct udevice *dev,
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struct phy_device *phydev)
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{
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struct bcm6348_eth_priv *priv = dev_get_priv(dev);
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/* mac duplex parameters */
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if (phydev->duplex)
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setbits_be32(priv->base + ETH_TXCTL_REG, ETH_TXCTL_FD_MASK);
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else
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clrbits_be32(priv->base + ETH_TXCTL_REG, ETH_TXCTL_FD_MASK);
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/* rx flow control (pause frame handling) */
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if (phydev->pause)
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setbits_be32(priv->base + ETH_RXCFG_REG,
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ETH_RXCFG_ENFLOW_MASK);
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else
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clrbits_be32(priv->base + ETH_RXCFG_REG,
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ETH_RXCFG_ENFLOW_MASK);
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return 0;
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}
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static int bcm6348_eth_start(struct udevice *dev)
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{
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struct bcm6348_eth_priv *priv = dev_get_priv(dev);
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int ret, i;
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/* prepare rx dma buffers */
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for (i = 0; i < ETH_RX_DESC; i++) {
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ret = dma_prepare_rcv_buf(&priv->rx_dma, net_rx_packets[i],
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PKTSIZE_ALIGN);
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if (ret < 0)
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break;
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}
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/* enable dma rx channel */
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dma_enable(&priv->rx_dma);
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/* enable dma tx channel */
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dma_enable(&priv->tx_dma);
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ret = phy_startup(priv->phy_dev);
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if (ret) {
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pr_err("%s: could not initialize phy\n", __func__);
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return ret;
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}
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if (!priv->phy_dev->link) {
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pr_err("%s: no phy link\n", __func__);
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return -EIO;
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}
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bcm6348_eth_adjust_link(dev, priv->phy_dev);
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/* zero mib counters */
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for (i = 0; i < MIB_REG_CNT; i++)
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writel_be(0, MIB_REG(i));
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/* enable rx flow control */
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setbits_be32(priv->base + ETH_RXCFG_REG, ETH_RXCFG_ENFLOW_MASK);
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/* set max rx/tx length */
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writel_be((ETH_MAX_MTU_SIZE << ETH_RXMAXLEN_SHIFT) &
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ETH_RXMAXLEN_MASK, priv->base + ETH_RXMAXLEN_REG);
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writel_be((ETH_MAX_MTU_SIZE << ETH_TXMAXLEN_SHIFT) &
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ETH_TXMAXLEN_MASK, priv->base + ETH_TXMAXLEN_REG);
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/* set correct transmit fifo watermark */
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writel_be((ETH_TX_WATERMARK << ETH_TXWMARK_WM_SHIFT) &
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ETH_TXWMARK_WM_MASK, priv->base + ETH_TXWMARK_REG);
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/* enable emac */
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bcm6348_eth_mac_enable(priv);
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/* clear interrupts */
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writel_be(0, priv->base + ETH_IRMASK_REG);
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return 0;
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}
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static void bcm6348_eth_stop(struct udevice *dev)
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{
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struct bcm6348_eth_priv *priv = dev_get_priv(dev);
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/* disable dma rx channel */
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dma_disable(&priv->rx_dma);
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/* disable dma tx channel */
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dma_disable(&priv->tx_dma);
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/* disable emac */
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bcm6348_eth_mac_disable(priv);
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}
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static int bcm6348_eth_write_hwaddr(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_platdata(dev);
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struct bcm6348_eth_priv *priv = dev_get_priv(dev);
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bool running = false;
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/* check if emac is running */
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if (readl_be(priv->base + ETH_CTL_REG) & ETH_CTL_ENABLE_MASK)
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running = true;
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/* disable emac */
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if (running)
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bcm6348_eth_mac_disable(priv);
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/* set mac address */
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writel_be((pdata->enetaddr[2] << 24) | (pdata->enetaddr[3]) << 16 |
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(pdata->enetaddr[4]) << 8 | (pdata->enetaddr[5]),
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priv->base + ETH_PML_REG(0));
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writel_be((pdata->enetaddr[1]) | (pdata->enetaddr[0] << 8) |
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ETH_PMH_VALID_MASK, priv->base + ETH_PMH_REG(0));
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/* enable emac */
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if (running)
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bcm6348_eth_mac_enable(priv);
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return 0;
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}
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static const struct eth_ops bcm6348_eth_ops = {
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.free_pkt = bcm6348_eth_free_pkt,
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.recv = bcm6348_eth_recv,
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.send = bcm6348_eth_send,
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.start = bcm6348_eth_start,
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.stop = bcm6348_eth_stop,
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.write_hwaddr = bcm6348_eth_write_hwaddr,
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};
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static const struct udevice_id bcm6348_eth_ids[] = {
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{ .compatible = "brcm,bcm6348-enet", },
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{ /* sentinel */ }
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};
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static int bcm6348_mdio_op(void __iomem *base, uint32_t data)
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{
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/* make sure mii interrupt status is cleared */
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writel_be(ETH_IR_MII_MASK, base + ETH_IR_REG);
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/* issue mii op */
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writel_be(data, base + MII_DAT_REG);
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/* wait until emac is disabled */
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return wait_for_bit_be32(base + ETH_IR_REG,
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ETH_IR_MII_MASK, true,
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ETH_TIMEOUT, false);
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}
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static int bcm6348_mdio_read(struct mii_dev *bus, int addr, int devaddr,
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int reg)
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{
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void __iomem *base = bus->priv;
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uint32_t val;
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val = MII_DAT_OP_READ;
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val |= (reg << MII_DAT_REG_SHIFT) & MII_DAT_REG_MASK;
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val |= (0x2 << MII_DAT_TA_SHIFT) & MII_DAT_TA_MASK;
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val |= (addr << MII_DAT_PHY_SHIFT) & MII_DAT_PHY_MASK;
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if (bcm6348_mdio_op(base, val)) {
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pr_err("%s: timeout\n", __func__);
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return -EINVAL;
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}
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val = readl_be(base + MII_DAT_REG) & MII_DAT_DATA_MASK;
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val >>= MII_DAT_DATA_SHIFT;
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return val;
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}
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static int bcm6348_mdio_write(struct mii_dev *bus, int addr, int dev_addr,
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int reg, u16 value)
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{
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void __iomem *base = bus->priv;
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uint32_t val;
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val = MII_DAT_OP_WRITE;
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val |= (reg << MII_DAT_REG_SHIFT) & MII_DAT_REG_MASK;
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val |= (0x2 << MII_DAT_TA_SHIFT) & MII_DAT_TA_MASK;
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val |= (addr << MII_DAT_PHY_SHIFT) & MII_DAT_PHY_MASK;
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val |= (value << MII_DAT_DATA_SHIFT) & MII_DAT_DATA_MASK;
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if (bcm6348_mdio_op(base, val)) {
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pr_err("%s: timeout\n", __func__);
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return -EINVAL;
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}
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return 0;
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}
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static int bcm6348_mdio_init(const char *name, void __iomem *base)
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{
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struct mii_dev *bus;
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bus = mdio_alloc();
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if (!bus) {
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pr_err("%s: failed to allocate MDIO bus\n", __func__);
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return -ENOMEM;
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}
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bus->read = bcm6348_mdio_read;
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bus->write = bcm6348_mdio_write;
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bus->priv = base;
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snprintf(bus->name, sizeof(bus->name), "%s", name);
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return mdio_register(bus);
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}
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static int bcm6348_phy_init(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_platdata(dev);
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struct bcm6348_eth_priv *priv = dev_get_priv(dev);
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struct mii_dev *bus;
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/* get mii bus */
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bus = miiphy_get_dev_by_name(dev->name);
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/* phy connect */
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priv->phy_dev = phy_connect(bus, priv->phy_id, dev,
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pdata->phy_interface);
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if (!priv->phy_dev) {
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pr_err("%s: no phy device\n", __func__);
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return -ENODEV;
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}
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priv->phy_dev->supported = (SUPPORTED_10baseT_Half |
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SUPPORTED_10baseT_Full |
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SUPPORTED_100baseT_Half |
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SUPPORTED_100baseT_Full |
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SUPPORTED_Autoneg |
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SUPPORTED_Pause |
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SUPPORTED_MII);
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priv->phy_dev->advertising = priv->phy_dev->supported;
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/* phy config */
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phy_config(priv->phy_dev);
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return 0;
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}
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static int bcm6348_eth_probe(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_platdata(dev);
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struct bcm6348_eth_priv *priv = dev_get_priv(dev);
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struct ofnode_phandle_args phy;
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const char *phy_mode;
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int ret, i;
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/* get base address */
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priv->base = dev_remap_addr(dev);
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if (!priv->base)
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return -EINVAL;
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pdata->iobase = (phys_addr_t) priv->base;
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/* get phy mode */
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pdata->phy_interface = PHY_INTERFACE_MODE_NONE;
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phy_mode = dev_read_string(dev, "phy-mode");
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if (phy_mode)
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pdata->phy_interface = phy_get_interface_by_name(phy_mode);
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if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
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return -ENODEV;
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/* get phy */
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if (dev_read_phandle_with_args(dev, "phy", NULL, 0, 0, &phy))
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return -ENOENT;
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priv->phy_id = ofnode_read_u32_default(phy.node, "reg", -1);
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/* get dma channels */
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ret = dma_get_by_name(dev, "tx", &priv->tx_dma);
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if (ret)
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return -EINVAL;
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ret = dma_get_by_name(dev, "rx", &priv->rx_dma);
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if (ret)
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return -EINVAL;
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/* try to enable clocks */
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for (i = 0; ; i++) {
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struct clk clk;
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int ret;
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ret = clk_get_by_index(dev, i, &clk);
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if (ret < 0)
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break;
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ret = clk_enable(&clk);
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if (ret < 0) {
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pr_err("%s: error enabling clock %d\n", __func__, i);
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return ret;
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}
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ret = clk_free(&clk);
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if (ret < 0) {
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pr_err("%s: error freeing clock %d\n", __func__, i);
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return ret;
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}
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}
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/* try to perform resets */
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for (i = 0; ; i++) {
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struct reset_ctl reset;
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int ret;
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ret = reset_get_by_index(dev, i, &reset);
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if (ret < 0)
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break;
|
|
|
|
ret = reset_deassert(&reset);
|
|
if (ret < 0) {
|
|
pr_err("%s: error deasserting reset %d\n", __func__, i);
|
|
return ret;
|
|
}
|
|
|
|
ret = reset_free(&reset);
|
|
if (ret < 0) {
|
|
pr_err("%s: error freeing reset %d\n", __func__, i);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
/* disable emac */
|
|
bcm6348_eth_mac_disable(priv);
|
|
|
|
/* reset emac */
|
|
bcm6348_eth_mac_reset(priv);
|
|
|
|
/* select correct mii interface */
|
|
if (pdata->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
|
|
clrbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_EPHY_MASK);
|
|
else
|
|
setbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_EPHY_MASK);
|
|
|
|
/* turn on mdc clock */
|
|
writel_be((0x1f << MII_SC_MDCFREQDIV_SHIFT) |
|
|
MII_SC_PREAMBLE_EN_MASK, priv->base + MII_SC_REG);
|
|
|
|
/* set mib counters to not clear when read */
|
|
clrbits_be32(priv->base + MIB_CTL_REG, MIB_CTL_RDCLEAR_MASK);
|
|
|
|
/* initialize perfect match registers */
|
|
for (i = 0; i < ETH_PM_CNT; i++) {
|
|
writel_be(0, priv->base + ETH_PML_REG(i));
|
|
writel_be(0, priv->base + ETH_PMH_REG(i));
|
|
}
|
|
|
|
/* init mii bus */
|
|
ret = bcm6348_mdio_init(dev->name, priv->base);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* init phy */
|
|
ret = bcm6348_phy_init(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
U_BOOT_DRIVER(bcm6348_eth) = {
|
|
.name = "bcm6348_eth",
|
|
.id = UCLASS_ETH,
|
|
.of_match = bcm6348_eth_ids,
|
|
.ops = &bcm6348_eth_ops,
|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
|
.priv_auto_alloc_size = sizeof(struct bcm6348_eth_priv),
|
|
.probe = bcm6348_eth_probe,
|
|
};
|