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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 13:23:20 +09:00
![Becky Bruce](/assets/img/avatar_default.png)
Change all code that conditionally operates on high bat registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS instead of the myriad ways this is done now. Define the option for every config for which high bats are supported (and enabled by early boot, on parts where they're not always enabled) Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
901 lines
19 KiB
ArmAsm
901 lines
19 KiB
ArmAsm
/*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
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* Copyright (C) 2001 Josh Huber <huber@mclx.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* U-Boot - Startup Code for PowerPC based Embedded Boards
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*
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*
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* The processor starts at 0xfff00100 and the code is executed
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* from flash. The code is organized to be at an other address
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* in memory, but as long we don't jump around before relocating.
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* board_init lies at a quite high address and when the cpu has
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* jumped there, everything is ok.
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*/
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#include <config.h>
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#include <74xx_7xx.h>
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#include <version.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#if !defined(CONFIG_DB64360) && \
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!defined(CONFIG_DB64460) && \
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!defined(CONFIG_CPCI750) && \
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!defined(CONFIG_P3Mx)
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#include <galileo/gt64260R.h>
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#endif
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#ifndef CONFIG_IDENT_STRING
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#define CONFIG_IDENT_STRING ""
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#endif
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/* We don't want the MMU yet.
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*/
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#undef MSR_KERNEL
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/* Machine Check and Recoverable Interr. */
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#define MSR_KERNEL ( MSR_ME | MSR_RI )
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/*
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* Set up GOT: Global Offset Table
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*
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* Use r14 to access the GOT
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*/
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START_GOT
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GOT_ENTRY(_GOT2_TABLE_)
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GOT_ENTRY(_FIXUP_TABLE_)
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GOT_ENTRY(_start)
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GOT_ENTRY(_start_of_vectors)
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GOT_ENTRY(_end_of_vectors)
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GOT_ENTRY(transfer_to_handler)
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GOT_ENTRY(__init_end)
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GOT_ENTRY(_end)
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GOT_ENTRY(__bss_start)
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END_GOT
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/*
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* r3 - 1st arg to board_init(): IMMP pointer
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* r4 - 2nd arg to board_init(): boot flag
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*/
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.text
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.long 0x27051956 /* U-Boot Magic Number */
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.globl version_string
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version_string:
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.ascii U_BOOT_VERSION
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.ascii " (", __DATE__, " - ", __TIME__, ")"
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.ascii CONFIG_IDENT_STRING, "\0"
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. = EXC_OFF_SYS_RESET
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.globl _start
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_start:
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li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
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b boot_cold
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sync
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. = EXC_OFF_SYS_RESET + 0x10
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.globl _start_warm
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_start_warm:
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li r21, BOOTFLAG_WARM /* Software reboot */
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b boot_warm
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sync
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/* the boot code is located below the exception table */
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.globl _start_of_vectors
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_start_of_vectors:
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/* Machine check */
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STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
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/* Data Storage exception. "Never" generated on the 860. */
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STD_EXCEPTION(0x300, DataStorage, UnknownException)
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/* Instruction Storage exception. "Never" generated on the 860. */
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STD_EXCEPTION(0x400, InstStorage, UnknownException)
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/* External Interrupt exception. */
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STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
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/* Alignment exception. */
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. = 0x600
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Alignment:
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EXCEPTION_PROLOG(SRR0, SRR1)
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mfspr r4,DAR
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stw r4,_DAR(r21)
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mfspr r5,DSISR
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stw r5,_DSISR(r21)
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addi r3,r1,STACK_FRAME_OVERHEAD
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li r20,MSR_KERNEL
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rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
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lwz r6,GOT(transfer_to_handler)
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mtlr r6
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blrl
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.L_Alignment:
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.long AlignmentException - _start + EXC_OFF_SYS_RESET
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.long int_return - _start + EXC_OFF_SYS_RESET
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/* Program check exception */
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. = 0x700
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ProgramCheck:
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EXCEPTION_PROLOG(SRR0, SRR1)
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addi r3,r1,STACK_FRAME_OVERHEAD
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li r20,MSR_KERNEL
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rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
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lwz r6,GOT(transfer_to_handler)
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mtlr r6
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blrl
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.L_ProgramCheck:
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.long ProgramCheckException - _start + EXC_OFF_SYS_RESET
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.long int_return - _start + EXC_OFF_SYS_RESET
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/* No FPU on MPC8xx. This exception is not supposed to happen.
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*/
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STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
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/* I guess we could implement decrementer, and may have
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* to someday for timekeeping.
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*/
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STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
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STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
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STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
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STD_EXCEPTION(0xc00, SystemCall, UnknownException)
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STD_EXCEPTION(0xd00, SingleStep, UnknownException)
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STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
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STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
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/*
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* On the MPC8xx, this is a software emulation interrupt. It
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* occurs for all unimplemented and illegal instructions.
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*/
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STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
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STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
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STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
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STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
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STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
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STD_EXCEPTION(0x1500, Reserved5, UnknownException)
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STD_EXCEPTION(0x1600, Reserved6, UnknownException)
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STD_EXCEPTION(0x1700, Reserved7, UnknownException)
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STD_EXCEPTION(0x1800, Reserved8, UnknownException)
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STD_EXCEPTION(0x1900, Reserved9, UnknownException)
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STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
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STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
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STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
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STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
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STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
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STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
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.globl _end_of_vectors
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_end_of_vectors:
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. = 0x2000
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boot_cold:
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boot_warm:
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/* disable everything */
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li r0, 0
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mtspr HID0, r0
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sync
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mtmsr 0
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bl invalidate_bats
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sync
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#ifdef CFG_L2
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/* init the L2 cache */
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addis r3, r0, L2_INIT@h
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ori r3, r3, L2_INIT@l
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sync
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mtspr l2cr, r3
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#endif
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#if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
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.long 0x7e00066c
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/*
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* dssall instruction, gas doesn't have it yet
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* ...for altivec, data stream stop all this probably
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* isn't needed unless we warm (software) reboot U-Boot
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*/
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#endif
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#ifdef CFG_L2
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/* invalidate the L2 cache */
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bl l2cache_invalidate
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sync
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#endif
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#ifdef CFG_BOARD_ASM_INIT
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/* do early init */
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bl board_asm_init
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#endif
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/*
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* Calculate absolute address in FLASH and jump there
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*------------------------------------------------------*/
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lis r3, CFG_MONITOR_BASE@h
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ori r3, r3, CFG_MONITOR_BASE@l
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addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
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mtlr r3
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blr
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in_flash:
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/* let the C-code set up the rest */
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/* */
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/* Be careful to keep code relocatable ! */
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/*------------------------------------------------------*/
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/* perform low-level init */
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/* sdram init, galileo init, etc */
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/* r3: NHR bit from HID0 */
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/* setup the bats */
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bl setup_bats
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sync
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/*
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* Cache must be enabled here for stack-in-cache trick.
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* This means we need to enable the BATS.
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* This means:
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* 1) for the EVB, original gt regs need to be mapped
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* 2) need to have an IBAT for the 0xf region,
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* we are running there!
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* Cache should be turned on after BATs, since by default
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* everything is write-through.
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* The init-mem BAT can be reused after reloc. The old
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* gt-regs BAT can be reused after board_init_f calls
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* board_early_init_f (EVB only).
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*/
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#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx)
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/* enable address translation */
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bl enable_addr_trans
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sync
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/* enable and invalidate the data cache */
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bl l1dcache_enable
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sync
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#endif
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#ifdef CFG_INIT_RAM_LOCK
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bl lock_ram_in_cache
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sync
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#endif
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/* set up the stack pointer in our newly created
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* cache-ram (r1) */
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lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
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ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
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li r0, 0 /* Make room for stack frame header and */
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stwu r0, -4(r1) /* clear final stack frame so that */
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stwu r0, -4(r1) /* stack backtraces terminate cleanly */
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GET_GOT /* initialize GOT access */
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/* run low-level CPU init code (from Flash) */
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bl cpu_init_f
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sync
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mr r3, r21
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/* r3: BOOTFLAG */
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/* run 1st part of board init code (from Flash) */
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bl board_init_f
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sync
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/* NOTREACHED */
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.globl invalidate_bats
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invalidate_bats:
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/* invalidate BATs */
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mtspr IBAT0U, r0
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mtspr IBAT1U, r0
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mtspr IBAT2U, r0
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mtspr IBAT3U, r0
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#ifdef CONFIG_HIGH_BATS
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mtspr IBAT4U, r0
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mtspr IBAT5U, r0
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mtspr IBAT6U, r0
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mtspr IBAT7U, r0
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#endif
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isync
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mtspr DBAT0U, r0
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mtspr DBAT1U, r0
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mtspr DBAT2U, r0
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mtspr DBAT3U, r0
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#ifdef CONFIG_HIGH_BATS
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mtspr DBAT4U, r0
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mtspr DBAT5U, r0
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mtspr DBAT6U, r0
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mtspr DBAT7U, r0
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#endif
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isync
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sync
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blr
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/* setup_bats - set them up to some initial state */
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.globl setup_bats
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setup_bats:
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addis r0, r0, 0x0000
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/* IBAT 0 */
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addis r4, r0, CFG_IBAT0L@h
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ori r4, r4, CFG_IBAT0L@l
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addis r3, r0, CFG_IBAT0U@h
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ori r3, r3, CFG_IBAT0U@l
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mtspr IBAT0L, r4
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mtspr IBAT0U, r3
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isync
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/* DBAT 0 */
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addis r4, r0, CFG_DBAT0L@h
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ori r4, r4, CFG_DBAT0L@l
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addis r3, r0, CFG_DBAT0U@h
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ori r3, r3, CFG_DBAT0U@l
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mtspr DBAT0L, r4
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mtspr DBAT0U, r3
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isync
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/* IBAT 1 */
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addis r4, r0, CFG_IBAT1L@h
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ori r4, r4, CFG_IBAT1L@l
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addis r3, r0, CFG_IBAT1U@h
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ori r3, r3, CFG_IBAT1U@l
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mtspr IBAT1L, r4
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mtspr IBAT1U, r3
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isync
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/* DBAT 1 */
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addis r4, r0, CFG_DBAT1L@h
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ori r4, r4, CFG_DBAT1L@l
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addis r3, r0, CFG_DBAT1U@h
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ori r3, r3, CFG_DBAT1U@l
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mtspr DBAT1L, r4
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mtspr DBAT1U, r3
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isync
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/* IBAT 2 */
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addis r4, r0, CFG_IBAT2L@h
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ori r4, r4, CFG_IBAT2L@l
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addis r3, r0, CFG_IBAT2U@h
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ori r3, r3, CFG_IBAT2U@l
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mtspr IBAT2L, r4
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mtspr IBAT2U, r3
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isync
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/* DBAT 2 */
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addis r4, r0, CFG_DBAT2L@h
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ori r4, r4, CFG_DBAT2L@l
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addis r3, r0, CFG_DBAT2U@h
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ori r3, r3, CFG_DBAT2U@l
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mtspr DBAT2L, r4
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mtspr DBAT2U, r3
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isync
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/* IBAT 3 */
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addis r4, r0, CFG_IBAT3L@h
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ori r4, r4, CFG_IBAT3L@l
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addis r3, r0, CFG_IBAT3U@h
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ori r3, r3, CFG_IBAT3U@l
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mtspr IBAT3L, r4
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mtspr IBAT3U, r3
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isync
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/* DBAT 3 */
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addis r4, r0, CFG_DBAT3L@h
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ori r4, r4, CFG_DBAT3L@l
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addis r3, r0, CFG_DBAT3U@h
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ori r3, r3, CFG_DBAT3U@l
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mtspr DBAT3L, r4
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mtspr DBAT3U, r3
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isync
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#ifdef CONFIG_HIGH_BATS
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/* IBAT 4 */
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addis r4, r0, CFG_IBAT4L@h
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ori r4, r4, CFG_IBAT4L@l
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addis r3, r0, CFG_IBAT4U@h
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ori r3, r3, CFG_IBAT4U@l
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mtspr IBAT4L, r4
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mtspr IBAT4U, r3
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isync
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/* DBAT 4 */
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addis r4, r0, CFG_DBAT4L@h
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ori r4, r4, CFG_DBAT4L@l
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addis r3, r0, CFG_DBAT4U@h
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ori r3, r3, CFG_DBAT4U@l
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mtspr DBAT4L, r4
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mtspr DBAT4U, r3
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isync
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/* IBAT 5 */
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addis r4, r0, CFG_IBAT5L@h
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ori r4, r4, CFG_IBAT5L@l
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addis r3, r0, CFG_IBAT5U@h
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ori r3, r3, CFG_IBAT5U@l
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mtspr IBAT5L, r4
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mtspr IBAT5U, r3
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isync
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/* DBAT 5 */
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addis r4, r0, CFG_DBAT5L@h
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ori r4, r4, CFG_DBAT5L@l
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addis r3, r0, CFG_DBAT5U@h
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ori r3, r3, CFG_DBAT5U@l
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mtspr DBAT5L, r4
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mtspr DBAT5U, r3
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isync
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/* IBAT 6 */
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addis r4, r0, CFG_IBAT6L@h
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ori r4, r4, CFG_IBAT6L@l
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addis r3, r0, CFG_IBAT6U@h
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ori r3, r3, CFG_IBAT6U@l
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mtspr IBAT6L, r4
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mtspr IBAT6U, r3
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isync
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/* DBAT 6 */
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addis r4, r0, CFG_DBAT6L@h
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ori r4, r4, CFG_DBAT6L@l
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addis r3, r0, CFG_DBAT6U@h
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ori r3, r3, CFG_DBAT6U@l
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mtspr DBAT6L, r4
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mtspr DBAT6U, r3
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isync
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/* IBAT 7 */
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addis r4, r0, CFG_IBAT7L@h
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ori r4, r4, CFG_IBAT7L@l
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addis r3, r0, CFG_IBAT7U@h
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ori r3, r3, CFG_IBAT7U@l
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mtspr IBAT7L, r4
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mtspr IBAT7U, r3
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isync
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/* DBAT 7 */
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addis r4, r0, CFG_DBAT7L@h
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ori r4, r4, CFG_DBAT7L@l
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addis r3, r0, CFG_DBAT7U@h
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ori r3, r3, CFG_DBAT7U@l
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mtspr DBAT7L, r4
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mtspr DBAT7U, r3
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isync
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#endif
|
|
|
|
/* bats are done, now invalidate the TLBs */
|
|
|
|
addis r3, 0, 0x0000
|
|
addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
|
|
|
|
isync
|
|
|
|
tlblp:
|
|
tlbie r3
|
|
sync
|
|
addi r3, r3, 0x1000
|
|
cmp 0, 0, r3, r5
|
|
blt tlblp
|
|
|
|
blr
|
|
|
|
.globl enable_addr_trans
|
|
enable_addr_trans:
|
|
/* enable address translation */
|
|
mfmsr r5
|
|
ori r5, r5, (MSR_IR | MSR_DR)
|
|
mtmsr r5
|
|
isync
|
|
blr
|
|
|
|
.globl disable_addr_trans
|
|
disable_addr_trans:
|
|
/* disable address translation */
|
|
mflr r4
|
|
mfmsr r3
|
|
andi. r0, r3, (MSR_IR | MSR_DR)
|
|
beqlr
|
|
andc r3, r3, r0
|
|
mtspr SRR0, r4
|
|
mtspr SRR1, r3
|
|
rfi
|
|
|
|
/*
|
|
* This code finishes saving the registers to the exception frame
|
|
* and jumps to the appropriate handler for the exception.
|
|
* Register r21 is pointer into trap frame, r1 has new stack pointer.
|
|
*/
|
|
.globl transfer_to_handler
|
|
transfer_to_handler:
|
|
stw r22,_NIP(r21)
|
|
lis r22,MSR_POW@h
|
|
andc r23,r23,r22
|
|
stw r23,_MSR(r21)
|
|
SAVE_GPR(7, r21)
|
|
SAVE_4GPRS(8, r21)
|
|
SAVE_8GPRS(12, r21)
|
|
SAVE_8GPRS(24, r21)
|
|
mflr r23
|
|
andi. r24,r23,0x3f00 /* get vector offset */
|
|
stw r24,TRAP(r21)
|
|
li r22,0
|
|
stw r22,RESULT(r21)
|
|
mtspr SPRG2,r22 /* r1 is now kernel sp */
|
|
lwz r24,0(r23) /* virtual address of handler */
|
|
lwz r23,4(r23) /* where to go when done */
|
|
mtspr SRR0,r24
|
|
mtspr SRR1,r20
|
|
mtlr r23
|
|
SYNC
|
|
rfi /* jump to handler, enable MMU */
|
|
|
|
int_return:
|
|
mfmsr r28 /* Disable interrupts */
|
|
li r4,0
|
|
ori r4,r4,MSR_EE
|
|
andc r28,r28,r4
|
|
SYNC /* Some chip revs need this... */
|
|
mtmsr r28
|
|
SYNC
|
|
lwz r2,_CTR(r1)
|
|
lwz r0,_LINK(r1)
|
|
mtctr r2
|
|
mtlr r0
|
|
lwz r2,_XER(r1)
|
|
lwz r0,_CCR(r1)
|
|
mtspr XER,r2
|
|
mtcrf 0xFF,r0
|
|
REST_10GPRS(3, r1)
|
|
REST_10GPRS(13, r1)
|
|
REST_8GPRS(23, r1)
|
|
REST_GPR(31, r1)
|
|
lwz r2,_NIP(r1) /* Restore environment */
|
|
lwz r0,_MSR(r1)
|
|
mtspr SRR0,r2
|
|
mtspr SRR1,r0
|
|
lwz r0,GPR0(r1)
|
|
lwz r2,GPR2(r1)
|
|
lwz r1,GPR1(r1)
|
|
SYNC
|
|
rfi
|
|
|
|
.globl dc_read
|
|
dc_read:
|
|
blr
|
|
|
|
.globl get_pvr
|
|
get_pvr:
|
|
mfspr r3, PVR
|
|
blr
|
|
|
|
/*-----------------------------------------------------------------------*/
|
|
/*
|
|
* void relocate_code (addr_sp, gd, addr_moni)
|
|
*
|
|
* This "function" does not return, instead it continues in RAM
|
|
* after relocating the monitor code.
|
|
*
|
|
* r3 = dest
|
|
* r4 = src
|
|
* r5 = length in bytes
|
|
* r6 = cachelinesize
|
|
*/
|
|
.globl relocate_code
|
|
relocate_code:
|
|
mr r1, r3 /* Set new stack pointer */
|
|
mr r9, r4 /* Save copy of Global Data pointer */
|
|
mr r10, r5 /* Save copy of Destination Address */
|
|
|
|
mr r3, r5 /* Destination Address */
|
|
lis r4, CFG_MONITOR_BASE@h /* Source Address */
|
|
ori r4, r4, CFG_MONITOR_BASE@l
|
|
lwz r5, GOT(__init_end)
|
|
sub r5, r5, r4
|
|
li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
|
|
|
|
/*
|
|
* Fix GOT pointer:
|
|
*
|
|
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
|
|
*
|
|
* Offset:
|
|
*/
|
|
sub r15, r10, r4
|
|
|
|
/* First our own GOT */
|
|
add r14, r14, r15
|
|
/* then the one used by the C code */
|
|
add r30, r30, r15
|
|
|
|
/*
|
|
* Now relocate code
|
|
*/
|
|
#ifdef CONFIG_ECC
|
|
bl board_relocate_rom
|
|
sync
|
|
mr r3, r10 /* Destination Address */
|
|
lis r4, CFG_MONITOR_BASE@h /* Source Address */
|
|
ori r4, r4, CFG_MONITOR_BASE@l
|
|
lwz r5, GOT(__init_end)
|
|
sub r5, r5, r4
|
|
li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
|
|
#else
|
|
cmplw cr1,r3,r4
|
|
addi r0,r5,3
|
|
srwi. r0,r0,2
|
|
beq cr1,4f /* In place copy is not necessary */
|
|
beq 7f /* Protect against 0 count */
|
|
mtctr r0
|
|
bge cr1,2f
|
|
|
|
la r8,-4(r4)
|
|
la r7,-4(r3)
|
|
1: lwzu r0,4(r8)
|
|
stwu r0,4(r7)
|
|
bdnz 1b
|
|
b 4f
|
|
|
|
2: slwi r0,r0,2
|
|
add r8,r4,r0
|
|
add r7,r3,r0
|
|
3: lwzu r0,-4(r8)
|
|
stwu r0,-4(r7)
|
|
bdnz 3b
|
|
#endif
|
|
/*
|
|
* Now flush the cache: note that we must start from a cache aligned
|
|
* address. Otherwise we might miss one cache line.
|
|
*/
|
|
4: cmpwi r6,0
|
|
add r5,r3,r5
|
|
beq 7f /* Always flush prefetch queue in any case */
|
|
subi r0,r6,1
|
|
andc r3,r3,r0
|
|
mr r4,r3
|
|
5: dcbst 0,r4
|
|
add r4,r4,r6
|
|
cmplw r4,r5
|
|
blt 5b
|
|
sync /* Wait for all dcbst to complete on bus */
|
|
mr r4,r3
|
|
6: icbi 0,r4
|
|
add r4,r4,r6
|
|
cmplw r4,r5
|
|
blt 6b
|
|
7: sync /* Wait for all icbi to complete on bus */
|
|
isync
|
|
|
|
/*
|
|
* We are done. Do not return, instead branch to second part of board
|
|
* initialization, now running from RAM.
|
|
*/
|
|
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
|
|
mtlr r0
|
|
blr
|
|
|
|
in_ram:
|
|
#ifdef CONFIG_ECC
|
|
bl board_init_ecc
|
|
#endif
|
|
/*
|
|
* Relocation Function, r14 point to got2+0x8000
|
|
*
|
|
* Adjust got2 pointers, no need to check for 0, this code
|
|
* already puts a few entries in the table.
|
|
*/
|
|
li r0,__got2_entries@sectoff@l
|
|
la r3,GOT(_GOT2_TABLE_)
|
|
lwz r11,GOT(_GOT2_TABLE_)
|
|
mtctr r0
|
|
sub r11,r3,r11
|
|
addi r3,r3,-4
|
|
1: lwzu r0,4(r3)
|
|
add r0,r0,r11
|
|
stw r0,0(r3)
|
|
bdnz 1b
|
|
|
|
/*
|
|
* Now adjust the fixups and the pointers to the fixups
|
|
* in case we need to move ourselves again.
|
|
*/
|
|
2: li r0,__fixup_entries@sectoff@l
|
|
lwz r3,GOT(_FIXUP_TABLE_)
|
|
cmpwi r0,0
|
|
mtctr r0
|
|
addi r3,r3,-4
|
|
beq 4f
|
|
3: lwzu r4,4(r3)
|
|
lwzux r0,r4,r11
|
|
add r0,r0,r11
|
|
stw r10,0(r3)
|
|
stw r0,0(r4)
|
|
bdnz 3b
|
|
4:
|
|
/* clear_bss: */
|
|
/*
|
|
* Now clear BSS segment
|
|
*/
|
|
lwz r3,GOT(__bss_start)
|
|
lwz r4,GOT(_end)
|
|
|
|
cmplw 0, r3, r4
|
|
beq 6f
|
|
|
|
li r0, 0
|
|
5:
|
|
stw r0, 0(r3)
|
|
addi r3, r3, 4
|
|
cmplw 0, r3, r4
|
|
bne 5b
|
|
6:
|
|
mr r3, r10 /* Destination Address */
|
|
#if defined(CONFIG_AMIGAONEG3SE) || \
|
|
defined(CONFIG_DB64360) || \
|
|
defined(CONFIG_DB64460) || \
|
|
defined(CONFIG_CPCI750) || \
|
|
defined(CONFIG_PPMC7XX) || \
|
|
defined(CONFIG_P3Mx)
|
|
mr r4, r9 /* Use RAM copy of the global data */
|
|
#endif
|
|
bl after_reloc
|
|
|
|
/* not reached - end relocate_code */
|
|
/*-----------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* Copy exception vector code to low memory
|
|
*
|
|
* r3: dest_addr
|
|
* r7: source address, r8: end address, r9: target address
|
|
*/
|
|
.globl trap_init
|
|
trap_init:
|
|
lwz r7, GOT(_start)
|
|
lwz r8, GOT(_end_of_vectors)
|
|
|
|
li r9, 0x100 /* reset vector always at 0x100 */
|
|
|
|
cmplw 0, r7, r8
|
|
bgelr /* return if r7>=r8 - just in case */
|
|
|
|
mflr r4 /* save link register */
|
|
1:
|
|
lwz r0, 0(r7)
|
|
stw r0, 0(r9)
|
|
addi r7, r7, 4
|
|
addi r9, r9, 4
|
|
cmplw 0, r7, r8
|
|
bne 1b
|
|
|
|
/*
|
|
* relocate `hdlr' and `int_return' entries
|
|
*/
|
|
li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
|
|
li r8, Alignment - _start + EXC_OFF_SYS_RESET
|
|
2:
|
|
bl trap_reloc
|
|
addi r7, r7, 0x100 /* next exception vector */
|
|
cmplw 0, r7, r8
|
|
blt 2b
|
|
|
|
li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
|
|
bl trap_reloc
|
|
|
|
li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
|
|
bl trap_reloc
|
|
|
|
li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
|
|
li r8, SystemCall - _start + EXC_OFF_SYS_RESET
|
|
3:
|
|
bl trap_reloc
|
|
addi r7, r7, 0x100 /* next exception vector */
|
|
cmplw 0, r7, r8
|
|
blt 3b
|
|
|
|
li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
|
|
li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
|
|
4:
|
|
bl trap_reloc
|
|
addi r7, r7, 0x100 /* next exception vector */
|
|
cmplw 0, r7, r8
|
|
blt 4b
|
|
|
|
/* enable execptions from RAM vectors */
|
|
mfmsr r7
|
|
li r8,MSR_IP
|
|
andc r7,r7,r8
|
|
mtmsr r7
|
|
|
|
mtlr r4 /* restore link register */
|
|
blr
|
|
|
|
/*
|
|
* Function: relocate entries for one exception vector
|
|
*/
|
|
trap_reloc:
|
|
lwz r0, 0(r7) /* hdlr ... */
|
|
add r0, r0, r3 /* ... += dest_addr */
|
|
stw r0, 0(r7)
|
|
|
|
lwz r0, 4(r7) /* int_return ... */
|
|
add r0, r0, r3 /* ... += dest_addr */
|
|
stw r0, 4(r7)
|
|
|
|
sync
|
|
isync
|
|
|
|
blr
|
|
|
|
#ifdef CFG_INIT_RAM_LOCK
|
|
lock_ram_in_cache:
|
|
/* Allocate Initial RAM in data cache.
|
|
*/
|
|
lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
|
|
ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
|
|
li r2, ((CFG_INIT_RAM_END & ~31) + \
|
|
(CFG_INIT_RAM_ADDR & 31) + 31) / 32
|
|
mtctr r2
|
|
1:
|
|
dcbz r0, r3
|
|
addi r3, r3, 32
|
|
bdnz 1b
|
|
|
|
/* Lock the data cache */
|
|
mfspr r0, HID0
|
|
ori r0, r0, 0x1000
|
|
sync
|
|
mtspr HID0, r0
|
|
sync
|
|
blr
|
|
|
|
.globl unlock_ram_in_cache
|
|
unlock_ram_in_cache:
|
|
/* invalidate the INIT_RAM section */
|
|
lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
|
|
ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
|
|
li r2, ((CFG_INIT_RAM_END & ~31) + \
|
|
(CFG_INIT_RAM_ADDR & 31) + 31) / 32
|
|
mtctr r2
|
|
1: icbi r0, r3
|
|
addi r3, r3, 32
|
|
bdnz 1b
|
|
sync /* Wait for all icbi to complete on bus */
|
|
isync
|
|
|
|
/* Unlock the data cache and invalidate it */
|
|
mfspr r0, HID0
|
|
li r3,0x1000
|
|
andc r0,r0,r3
|
|
li r3,0x0400
|
|
or r0,r0,r3
|
|
sync
|
|
mtspr HID0, r0
|
|
sync
|
|
blr
|
|
#endif
|