mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-18 17:18:01 +09:00
70f5c99d60
This currently hangs and it is not necessary in any case. Drop the code when booting from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
40 lines
737 B
C
40 lines
737 B
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* (C) Copyright 2011
|
|
* Graeme Russ, <graeme.russ@gmail.com>
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <init.h>
|
|
#include <asm/global_data.h>
|
|
#include <linux/errno.h>
|
|
#include <asm/mtrr.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
int init_cache_f_r(void)
|
|
{
|
|
bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) ||
|
|
IS_ENABLED(CONFIG_FSP_VERSION2);
|
|
int ret;
|
|
|
|
if (!ll_boot_init())
|
|
return 0;
|
|
|
|
do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
|
|
!IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
|
|
|
|
if (do_mtrr) {
|
|
ret = mtrr_commit(false);
|
|
/*
|
|
* If MTRR MSR is not implemented by the processor, just ignore
|
|
* it
|
|
*/
|
|
if (ret && ret != -ENOSYS)
|
|
return ret;
|
|
}
|
|
|
|
/* Initialise the CPU cache(s) */
|
|
return init_cache();
|
|
}
|