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https://github.com/brain-hackers/u-boot-brain
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ffd06e0231
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
22 lines
518 B
C
22 lines
518 B
C
#ifndef __MPC85XX_MP_H_
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#define __MPC85XX_MP_H_
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#include <asm/mp.h>
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phys_addr_t get_spin_phys_addr(void);
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u32 get_my_id(void);
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int hold_cores_in_reset(int verbose);
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#define BOOT_ENTRY_ADDR_UPPER 0
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#define BOOT_ENTRY_ADDR_LOWER 1
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#define BOOT_ENTRY_R3_UPPER 2
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#define BOOT_ENTRY_R3_LOWER 3
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#define BOOT_ENTRY_RESV 4
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#define BOOT_ENTRY_PIR 5
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#define BOOT_ENTRY_R6_UPPER 6
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#define BOOT_ENTRY_R6_LOWER 7
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#define NUM_BOOT_ENTRY 16 /* pad to 64 bytes */
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#define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32))
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#endif
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