Dave Liu 22ff3d0134 fsl-ddr: clean up the ddr code for DDR3 controller ... - The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>		2009-01-23 17:03:13 -06:00
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ddr	fsl-ddr: clean up the ddr code for DDR3 controller	2009-01-23 17:03:13 -06:00