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228f9e0244
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register access, the other for the qspi core and phy. Both are mandatory. Enable the qspi node together with the SST26VF064B qspi nor flash memory. Booting from the QSPI NOR flash is now possible. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
56 lines
1.2 KiB
Plaintext
56 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sam9x60ek.dts - Device Tree file for SAM9X60 EK board
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*
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* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Sandeep Sheriker M <Sandeepsheriker.mallikarjun@microchip.com>
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*/
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/dts-v1/;
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#include "sam9x60.dtsi"
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/ {
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model = "Microchip SAM9X60-Ek";
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compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9";
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chosen {
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stdout-path = &dbgu;
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};
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ahb {
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apb {
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qspi: spi@f0014000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi>;
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status = "okay";
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nor_flash: sst26vf064@0 {
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compatible = "spi-flash";
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reg = <0>;
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spi-max-frequency = <80000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <4>;
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};
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};
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pinctrl {
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pinctrl_qspi: qspi {
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atmel,pins =
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<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
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AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE
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AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
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AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
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AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
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AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
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};
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};
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};
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};
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};
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&macb0 {
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phy-mode = "rmii";
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status = "okay";
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};
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