mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 05:13:21 +09:00
![Simon Glass](/assets/img/avatar_default.png)
Add the requires settings to enable SATA on link. Signed-off-by: Simon Glass <sjg@chromium.org>
212 lines
4.7 KiB
Plaintext
212 lines
4.7 KiB
Plaintext
/dts-v1/;
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/include/ "coreboot.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Google Link";
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compatible = "google,link", "intel,celeron-ivybridge";
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config {
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silent_console = <0>;
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};
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gpioa {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0 0x10>;
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bank-name = "A";
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};
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gpiob {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x30 0x10>;
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bank-name = "B";
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};
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gpioc {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x40 0x10>;
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bank-name = "C";
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};
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serial {
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reg = <0x3f8 8>;
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clock-frequency = <115200>;
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};
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chosen { };
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memory { device_type = "memory"; reg = <0 0>; };
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spd {
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compatible = "memory-spd";
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#address-cells = <1>;
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#size-cells = <0>;
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elpida_4Gb_1600_x16 {
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reg = <0>;
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data = [92 10 0b 03 04 19 02 02
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03 52 01 08 0a 00 fe 00
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69 78 69 3c 69 11 18 81
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20 08 3c 3c 01 40 83 81
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 0f 11 42 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 02 fe 00
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11 52 00 00 00 07 7f 37
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45 42 4a 32 30 55 47 36
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45 42 55 30 2d 47 4e 2d
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46 20 30 20 02 fe 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00];
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};
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samsung_4Gb_1600_1.35v_x16 {
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reg = <1>;
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data = [92 11 0b 03 04 19 02 02
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03 11 01 08 0a 00 fe 00
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69 78 69 3c 69 11 18 81
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f0 0a 3c 3c 01 40 83 01
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00 80 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 0f 11 02 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 80 ce 01
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00 00 00 00 00 00 6a 04
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4d 34 37 31 42 35 36 37
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34 42 48 30 2d 59 4b 30
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20 20 00 00 80 ce 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00];
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};
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micron_4Gb_1600_1.35v_x16 {
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reg = <2>;
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data = [92 11 0b 03 04 19 02 02
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03 11 01 08 0a 00 fe 00
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69 78 69 3c 69 11 18 81
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20 08 3c 3c 01 40 83 05
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 0f 01 02 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 80 2c 00
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00 00 00 00 00 00 ad 75
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34 4b 54 46 32 35 36 36
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34 48 5a 2d 31 47 36 45
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31 20 45 31 80 2c 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff];
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};
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};
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich9";
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spi-flash@0 {
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reg = <0>;
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compatible = "winbond,w25q64", "spi-flash";
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memory-map = <0xff800000 0x00800000>;
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};
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};
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pci {
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sata {
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compatible = "intel,pantherpoint-ahci";
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intel,sata-mode = "ahci";
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intel,sata-port-map = <1>;
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intel,sata-port0-gen3-tx = <0x00880a7f>;
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};
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lpc {
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compatible = "intel,lpc";
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#address-cells = <1>;
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#size-cells = <1>;
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gen-dec = <0x800 0xfc 0x900 0xfc>;
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intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
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intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
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0x80 0x80 0x80 0x80>;
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intel,gpi-routing = <0 0 0 0 0 0 0 2
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1 0 0 0 0 0 0 0>;
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/* Enable EC SMI source */
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intel,alt-gp-smi-enable = <0x0100>;
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cros-ec@200 {
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compatible = "google,cros-ec";
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reg = <0x204 1 0x200 1 0x880 0x80>;
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/* Describes the flash memory within the EC */
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#address-cells = <1>;
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#size-cells = <1>;
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flash@8000000 {
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reg = <0x08000000 0x20000>;
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erase-value = <0xff>;
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};
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};
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};
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};
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microcode {
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update@0 {
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#include "m12206a7_00000028.dtsi"
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};
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update@1 {
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#include "m12306a9_00000017.dtsi"
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};
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};
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};
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