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22452fd821
The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return instead of configuring the SATA clock and GPR13 registers. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
40 lines
928 B
C
40 lines
928 B
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/arch/iomux.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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int setup_sata(void)
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{
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struct iomuxc_base_regs *const iomuxc_regs
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= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
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int ret;
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if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
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return 1;
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ret = enable_sata_clock();
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if (ret)
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return ret;
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clrsetbits_le32(&iomuxc_regs->gpr[13],
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IOMUXC_GPR13_SATA_MASK,
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IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
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|IOMUXC_GPR13_SATA_PHY_7_SATA2M
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|IOMUXC_GPR13_SATA_SPEED_3G
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|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
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|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
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|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
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|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
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|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
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|IOMUXC_GPR13_SATA_PHY_1_SLOW);
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return 0;
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}
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