mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
510 lines
11 KiB
C
510 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* TI DaVinci (TMS320DM644x) I2C driver.
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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* (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
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* --------------------------------------------------------
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*
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* NOTE: This driver should be converted to driver model before June 2017.
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* Please see doc/driver-model/i2c-howto.txt for instructions.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <dm.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/i2c_defs.h>
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#include <asm/io.h>
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#include "davinci_i2c.h"
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#ifdef CONFIG_DM_I2C
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/* Information about i2c controller */
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struct i2c_bus {
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int id;
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uint speed;
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struct i2c_regs *regs;
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};
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#endif
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#define CHECK_NACK() \
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do {\
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if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
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REG(&(i2c_base->i2c_con)) = 0;\
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return 1;\
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} \
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} while (0)
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static int _wait_for_bus(struct i2c_regs *i2c_base)
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{
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int stat, timeout;
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REG(&(i2c_base->i2c_stat)) = 0xffff;
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for (timeout = 0; timeout < 10; timeout++) {
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stat = REG(&(i2c_base->i2c_stat));
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if (!((stat) & I2C_STAT_BB)) {
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REG(&(i2c_base->i2c_stat)) = 0xffff;
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return 0;
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}
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REG(&(i2c_base->i2c_stat)) = stat;
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udelay(50000);
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}
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REG(&(i2c_base->i2c_stat)) = 0xffff;
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return 1;
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}
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static int _poll_i2c_irq(struct i2c_regs *i2c_base, int mask)
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{
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int stat, timeout;
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for (timeout = 0; timeout < 10; timeout++) {
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udelay(1000);
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stat = REG(&(i2c_base->i2c_stat));
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if (stat & mask)
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return stat;
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}
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REG(&(i2c_base->i2c_stat)) = 0xffff;
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return stat | I2C_TIMEOUT;
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}
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static void _flush_rx(struct i2c_regs *i2c_base)
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{
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while (1) {
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if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
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break;
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REG(&(i2c_base->i2c_drr));
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REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY;
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udelay(1000);
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}
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}
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static uint _davinci_i2c_setspeed(struct i2c_regs *i2c_base,
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uint speed)
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{
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uint32_t div, psc;
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psc = 2;
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/* SCLL + SCLH */
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div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
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REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
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REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
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REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
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return 0;
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}
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static void _davinci_i2c_init(struct i2c_regs *i2c_base,
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uint speed, int slaveadd)
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{
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if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
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REG(&(i2c_base->i2c_con)) = 0;
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udelay(50000);
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}
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_davinci_i2c_setspeed(i2c_base, speed);
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REG(&(i2c_base->i2c_oa)) = slaveadd;
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REG(&(i2c_base->i2c_cnt)) = 0;
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/* Interrupts must be enabled or I2C module won't work */
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REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
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I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
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/* Now enable I2C controller (get it out of reset) */
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REG(&(i2c_base->i2c_con)) = I2C_CON_EN;
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udelay(1000);
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}
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static int _davinci_i2c_read(struct i2c_regs *i2c_base, uint8_t chip,
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uint32_t addr, int alen, uint8_t *buf, int len)
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{
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uint32_t tmp;
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int i;
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if ((alen < 0) || (alen > 2)) {
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printf("%s(): bogus address length %x\n", __func__, alen);
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return 1;
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}
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if (_wait_for_bus(i2c_base))
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return 1;
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if (alen != 0) {
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/* Start address phase */
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tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
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REG(&(i2c_base->i2c_cnt)) = alen;
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REG(&(i2c_base->i2c_sa)) = chip;
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REG(&(i2c_base->i2c_con)) = tmp;
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tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
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CHECK_NACK();
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switch (alen) {
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case 2:
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/* Send address MSByte */
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if (tmp & I2C_STAT_XRDY) {
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REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
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} else {
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REG(&(i2c_base->i2c_con)) = 0;
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return 1;
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}
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tmp = _poll_i2c_irq(i2c_base,
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I2C_STAT_XRDY | I2C_STAT_NACK);
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CHECK_NACK();
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/* No break, fall through */
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case 1:
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/* Send address LSByte */
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if (tmp & I2C_STAT_XRDY) {
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REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
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} else {
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REG(&(i2c_base->i2c_con)) = 0;
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return 1;
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}
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tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY |
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I2C_STAT_NACK | I2C_STAT_ARDY);
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CHECK_NACK();
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if (!(tmp & I2C_STAT_ARDY)) {
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REG(&(i2c_base->i2c_con)) = 0;
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return 1;
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}
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}
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}
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/* Address phase is over, now read 'len' bytes and stop */
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tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
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REG(&(i2c_base->i2c_cnt)) = len & 0xffff;
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REG(&(i2c_base->i2c_sa)) = chip;
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REG(&(i2c_base->i2c_con)) = tmp;
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for (i = 0; i < len; i++) {
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tmp = _poll_i2c_irq(i2c_base, I2C_STAT_RRDY | I2C_STAT_NACK |
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I2C_STAT_ROVR);
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CHECK_NACK();
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if (tmp & I2C_STAT_RRDY) {
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buf[i] = REG(&(i2c_base->i2c_drr));
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} else {
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REG(&(i2c_base->i2c_con)) = 0;
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return 1;
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}
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}
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tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK);
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CHECK_NACK();
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if (!(tmp & I2C_STAT_SCD)) {
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REG(&(i2c_base->i2c_con)) = 0;
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return 1;
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}
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_flush_rx(i2c_base);
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REG(&(i2c_base->i2c_stat)) = 0xffff;
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REG(&(i2c_base->i2c_cnt)) = 0;
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REG(&(i2c_base->i2c_con)) = 0;
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return 0;
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}
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static int _davinci_i2c_write(struct i2c_regs *i2c_base, uint8_t chip,
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uint32_t addr, int alen, uint8_t *buf, int len)
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{
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uint32_t tmp;
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int i;
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if ((alen < 0) || (alen > 2)) {
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printf("%s(): bogus address length %x\n", __func__, alen);
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return 1;
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}
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if (len < 0) {
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printf("%s(): bogus length %x\n", __func__, len);
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return 1;
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}
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if (_wait_for_bus(i2c_base))
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return 1;
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/* Start address phase */
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tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
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I2C_CON_TRX | I2C_CON_STP;
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REG(&(i2c_base->i2c_cnt)) = (alen == 0) ?
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len & 0xffff : (len & 0xffff) + alen;
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REG(&(i2c_base->i2c_sa)) = chip;
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REG(&(i2c_base->i2c_con)) = tmp;
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switch (alen) {
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case 2:
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/* Send address MSByte */
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tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
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CHECK_NACK();
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if (tmp & I2C_STAT_XRDY) {
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REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
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} else {
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REG(&(i2c_base->i2c_con)) = 0;
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return 1;
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}
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/* No break, fall through */
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case 1:
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/* Send address LSByte */
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tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
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CHECK_NACK();
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if (tmp & I2C_STAT_XRDY) {
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REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
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} else {
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REG(&(i2c_base->i2c_con)) = 0;
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return 1;
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}
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}
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for (i = 0; i < len; i++) {
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tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
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CHECK_NACK();
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if (tmp & I2C_STAT_XRDY)
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REG(&(i2c_base->i2c_dxr)) = buf[i];
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else
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return 1;
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}
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tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK);
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CHECK_NACK();
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if (!(tmp & I2C_STAT_SCD)) {
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REG(&(i2c_base->i2c_con)) = 0;
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return 1;
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}
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_flush_rx(i2c_base);
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REG(&(i2c_base->i2c_stat)) = 0xffff;
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REG(&(i2c_base->i2c_cnt)) = 0;
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REG(&(i2c_base->i2c_con)) = 0;
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return 0;
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}
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static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip)
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{
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int rc = 1;
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if (chip == REG(&(i2c_base->i2c_oa)))
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return rc;
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REG(&(i2c_base->i2c_con)) = 0;
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if (_wait_for_bus(i2c_base))
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return 1;
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/* try to read one byte from current (or only) address */
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REG(&(i2c_base->i2c_cnt)) = 1;
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REG(&(i2c_base->i2c_sa)) = chip;
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REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
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I2C_CON_STP);
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udelay(50000);
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if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
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rc = 0;
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_flush_rx(i2c_base);
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REG(&(i2c_base->i2c_stat)) = 0xffff;
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} else {
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REG(&(i2c_base->i2c_stat)) = 0xffff;
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REG(&(i2c_base->i2c_con)) |= I2C_CON_STP;
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udelay(20000);
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if (_wait_for_bus(i2c_base))
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return 1;
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}
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_flush_rx(i2c_base);
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REG(&(i2c_base->i2c_stat)) = 0xffff;
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REG(&(i2c_base->i2c_cnt)) = 0;
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return rc;
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}
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#ifndef CONFIG_DM_I2C
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static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
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{
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switch (adap->hwadapnr) {
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#if CONFIG_SYS_I2C_BUS_MAX >= 3
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case 2:
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return (struct i2c_regs *)I2C2_BASE;
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 2
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case 1:
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return (struct i2c_regs *)I2C1_BASE;
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#endif
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case 0:
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return (struct i2c_regs *)I2C_BASE;
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default:
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printf("wrong hwadapnr: %d\n", adap->hwadapnr);
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}
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return NULL;
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}
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static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
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{
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struct i2c_regs *i2c_base = davinci_get_base(adap);
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uint ret;
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adap->speed = speed;
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ret = _davinci_i2c_setspeed(i2c_base, speed);
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return ret;
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}
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static void davinci_i2c_init(struct i2c_adapter *adap, int speed,
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int slaveadd)
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{
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struct i2c_regs *i2c_base = davinci_get_base(adap);
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adap->speed = speed;
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_davinci_i2c_init(i2c_base, speed, slaveadd);
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return;
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}
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static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
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uint32_t addr, int alen, uint8_t *buf, int len)
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{
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struct i2c_regs *i2c_base = davinci_get_base(adap);
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return _davinci_i2c_read(i2c_base, chip, addr, alen, buf, len);
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}
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static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
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uint32_t addr, int alen, uint8_t *buf, int len)
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{
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struct i2c_regs *i2c_base = davinci_get_base(adap);
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return _davinci_i2c_write(i2c_base, chip, addr, alen, buf, len);
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}
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static int davinci_i2c_probe_chip(struct i2c_adapter *adap, uint8_t chip)
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{
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struct i2c_regs *i2c_base = davinci_get_base(adap);
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return _davinci_i2c_probe_chip(i2c_base, chip);
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}
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U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe_chip,
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davinci_i2c_read, davinci_i2c_write,
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davinci_i2c_setspeed,
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CONFIG_SYS_DAVINCI_I2C_SPEED,
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CONFIG_SYS_DAVINCI_I2C_SLAVE,
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0)
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#if CONFIG_SYS_I2C_BUS_MAX >= 2
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U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip,
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davinci_i2c_read, davinci_i2c_write,
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davinci_i2c_setspeed,
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CONFIG_SYS_DAVINCI_I2C_SPEED1,
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CONFIG_SYS_DAVINCI_I2C_SLAVE1,
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1)
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 3
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U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe_chip,
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davinci_i2c_read, davinci_i2c_write,
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davinci_i2c_setspeed,
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CONFIG_SYS_DAVINCI_I2C_SPEED2,
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CONFIG_SYS_DAVINCI_I2C_SLAVE2,
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2)
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#endif
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#else /* CONFIG_DM_I2C */
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static int davinci_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
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int nmsgs)
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{
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struct i2c_bus *i2c_bus = dev_get_priv(bus);
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int ret;
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debug("i2c_xfer: %d messages\n", nmsgs);
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for (; nmsgs > 0; nmsgs--, msg++) {
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debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
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if (msg->flags & I2C_M_RD) {
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ret = _davinci_i2c_read(i2c_bus->regs, msg->addr,
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0, 0, msg->buf, msg->len);
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} else {
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ret = _davinci_i2c_write(i2c_bus->regs, msg->addr,
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0, 0, msg->buf, msg->len);
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}
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if (ret) {
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debug("i2c_write: error sending\n");
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return -EREMOTEIO;
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}
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}
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return ret;
|
|
}
|
|
|
|
static int davinci_i2c_set_speed(struct udevice *dev, uint speed)
|
|
{
|
|
struct i2c_bus *i2c_bus = dev_get_priv(dev);
|
|
|
|
i2c_bus->speed = speed;
|
|
return _davinci_i2c_setspeed(i2c_bus->regs, speed);
|
|
}
|
|
|
|
static int davinci_i2c_probe(struct udevice *dev)
|
|
{
|
|
struct i2c_bus *i2c_bus = dev_get_priv(dev);
|
|
|
|
i2c_bus->id = dev->seq;
|
|
i2c_bus->regs = (struct i2c_regs *)devfdt_get_addr(dev);
|
|
|
|
i2c_bus->speed = 100000;
|
|
_davinci_i2c_init(i2c_bus->regs, i2c_bus->speed, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int davinci_i2c_probe_chip(struct udevice *bus, uint chip_addr,
|
|
uint chip_flags)
|
|
{
|
|
struct i2c_bus *i2c_bus = dev_get_priv(bus);
|
|
|
|
return _davinci_i2c_probe_chip(i2c_bus->regs, chip_addr);
|
|
}
|
|
|
|
static const struct dm_i2c_ops davinci_i2c_ops = {
|
|
.xfer = davinci_i2c_xfer,
|
|
.probe_chip = davinci_i2c_probe_chip,
|
|
.set_bus_speed = davinci_i2c_set_speed,
|
|
};
|
|
|
|
static const struct udevice_id davinci_i2c_ids[] = {
|
|
{ .compatible = "ti,davinci-i2c"},
|
|
{ .compatible = "ti,keystone-i2c"},
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(i2c_davinci) = {
|
|
.name = "i2c_davinci",
|
|
.id = UCLASS_I2C,
|
|
.of_match = davinci_i2c_ids,
|
|
.probe = davinci_i2c_probe,
|
|
.priv_auto_alloc_size = sizeof(struct i2c_bus),
|
|
.ops = &davinci_i2c_ops,
|
|
};
|
|
|
|
#endif /* CONFIG_DM_I2C */
|