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https://github.com/brain-hackers/u-boot-brain
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222a3113b4
PISMO_xx macros were used to define 'Platform Independent Storage MOdule'
related GPMC configurations. This patch
- Replaces these OMAP3 specific macros with generic CONFIG_xx macros as provided
by current u-boot infrastructure.
- Removes unused redundant macros, which are no longer required after
merging of common platform code in following commit
commit a0a37183bd
ARM: omap: merge GPMC initialization code for all platform
+-----------------+-----------------------------------------------------------+
| Macro | Reason for removal |
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR_BASE | duplicate of CONFIG_SYS_FLASH_BASE |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_BASE| duplicate of CONFIG_SYS_NAND_BASE |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_BASE| duplicate of CONFIG_SYS_ONENAND_BASE |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_SIZE| GPMC accesses NAND device via I/O mapped registers so |
| | configuring GPMC chip-select for smallest allowable |
| | segment (GPMC_SIZE_16M) is enough. |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_SIZE| OneNAND uses a fixed GPMC chip-select address-space of |
| | 128MB (GPMC_SIZE_128M) |
+-----------------+-----------------------------------------------------------+
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR | Unused Macros |
| PISMO1_NAND | |
| PISMO2_CS0 | |
| PISMO2_CS1 | |
| PISMO1_ONENAND | |
| PISMO2_NAND_CS0 | |
| PISMO2_NAND_CS1 | |
| PISMO1_NOR_BASE | |
| PISMO1_NAND_BASE| |
| PISMO2_CS0_BASE | |
+-----------------+-----------------------------------------------------------+
Signed-off-by: Pekon Gupta <pekon@ti.com>
202 lines
5.4 KiB
C
202 lines
5.4 KiB
C
/*
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* Common configuration settings for IGEP technology based boards
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*
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* (C) Copyright 2012
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* ISEE 2007 SL, <www.iseebcn.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __IGEP00X0_H
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#define __IGEP00X0_H
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#ifdef CONFIG_BOOT_NAND
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#define CONFIG_NAND
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#endif
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#define CONFIG_NR_DRAM_BANKS 2
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#include <configs/ti_omap3_common.h>
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#include <asm/mach-types.h>
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/*
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* Display CPU and Board information
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*/
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#define CONFIG_DISPLAY_CPUINFO 1
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#define CONFIG_DISPLAY_BOARDINFO 1
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#define CONFIG_MISC_INIT_R
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#define CONFIG_REVISION_TAG 1
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#define CONFIG_SUPPORT_RAW_INITRD
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/* define to enable boot progress via leds */
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#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
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(CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
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#define CONFIG_SHOW_BOOT_PROGRESS
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#endif
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/* GPIO banks */
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#define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */
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#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
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#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
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/* USB */
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#define CONFIG_MUSB_UDC 1
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#define CONFIG_USB_OMAP3 1
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#define CONFIG_TWL4030_USB 1
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/* USB device configuration */
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#define CONFIG_USB_DEVICE 1
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#define CONFIG_USB_TTY 1
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
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/* Change these to suit your needs */
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#define CONFIG_USBD_VENDORID 0x0451
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#define CONFIG_USBD_PRODUCTID 0x5678
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#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
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#define CONFIG_USBD_PRODUCT_NAME "IGEP"
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#define CONFIG_CMD_CACHE
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#ifdef CONFIG_BOOT_ONENAND
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#define CONFIG_CMD_ONENAND /* ONENAND support */
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#endif
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#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
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(CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
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#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
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#endif
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_NFS /* NFS support */
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/*#undef CONFIG_ENV_IS_NOWHERE*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"usbtty=cdc_acm\0" \
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"loadaddr=0x82000000\0" \
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"dtbaddr=0x81600000\0" \
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"bootdir=/boot\0" \
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"bootfile=zImage\0" \
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"usbtty=cdc_acm\0" \
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"console=ttyO2,115200n8\0" \
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"mpurate=auto\0" \
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"vram=12M\0" \
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"dvimode=1024x768MR-16@60\0" \
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"defaultdisplay=dvi\0" \
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"mmcdev=0\0" \
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"mmcroot=/dev/mmcblk0p2 rw\0" \
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"mmcrootfstype=ext4 rootwait\0" \
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"nandroot=/dev/mtdblock4 rw\0" \
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"nandrootfstype=jffs2\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"mpurate=${mpurate} " \
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"vram=${vram} " \
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"omapfb.mode=dvi:${dvimode} " \
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"omapfb.debug=y " \
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"omapdss.def_disp=${defaultdisplay} " \
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"root=${mmcroot} " \
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"rootfstype=${mmcrootfstype}\0" \
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"nandargs=setenv bootargs console=${console} " \
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"mpurate=${mpurate} " \
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"vram=${vram} " \
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"omapfb.mode=dvi:${dvimode} " \
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"omapfb.debug=y " \
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"omapdss.def_disp=${defaultdisplay} " \
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"root=${nandroot} " \
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"rootfstype=${nandrootfstype}\0" \
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"loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
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"importbootenv=echo Importing environment from mmc ...; " \
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"env import -t $loadaddr $filesize\0" \
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"loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
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"loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"bootz ${loadaddr}\0" \
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"mmcbootfdt=echo Booting with DT from mmc ...; " \
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"bootz ${loadaddr} - ${dtbaddr}\0" \
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"nandboot=echo Booting from onenand ...; " \
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"run nandargs; " \
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"onenand read ${loadaddr} 280000 400000; " \
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"bootz ${loadaddr}\0" \
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"echo SD/MMC found on device ${mmcdev};" \
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"if run loadbootenv; then " \
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"run importbootenv;" \
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"fi;" \
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"if test -n $uenvcmd; then " \
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"echo Running uenvcmd ...;" \
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"run uenvcmd;" \
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"fi;" \
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"if run loadzimage; then " \
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"if test -n $dtbfile; then " \
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"if run loadfdt; then " \
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"run mmcbootfdt;" \
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"fi;" \
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"fi;" \
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"run mmcboot;" \
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"fi;" \
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"fi;" \
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"run nandboot;" \
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/*
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* FLASH and environment organization
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*/
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#ifdef CONFIG_BOOT_ONENAND
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#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
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#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
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#define CONFIG_ENV_IS_IN_ONENAND 1
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#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
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#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
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#endif
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#ifdef CONFIG_NAND
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#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
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#define CONFIG_ENV_IS_IN_NAND 1
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#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
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#define CONFIG_ENV_ADDR NAND_ENV_OFFSET
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#endif
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/*
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* SMSC911x Ethernet
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*/
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_SMC911X
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#define CONFIG_SMC911X_32_BIT
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#define CONFIG_SMC911X_BASE 0x2C000000
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#endif /* (CONFIG_CMD_NET) */
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/* OneNAND boot config */
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#ifdef CONFIG_BOOT_ONENAND
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#define CONFIG_SPL_ONENAND_SUPPORT
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#define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000
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#define CONFIG_SYS_ONENAND_PAGE_SIZE 2048
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#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000
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#define CONFIG_SPL_ONENAND_LOAD_SIZE \
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(512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
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#endif
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/* NAND boot config */
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#ifdef CONFIG_NAND
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#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#endif
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#endif /* __IGEP00X0_H */
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