mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-16 23:18:51 +09:00
![Yangbo Lu](/assets/img/avatar_default.png)
Converted to use fsl_esdhc_imx for i.MX platforms. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Martyn Welch <martyn.welch@collabora.com> Acked-by: Jason Liu <Jason.hui.liu@nxp.com>
273 lines
7.3 KiB
C
273 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014 Soeren Moch <smoch@web.de>
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/video.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_SRE_SLOW)
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart2_pads[] = {
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MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const enet_pads[] = {
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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/* AR8035 PHY Reset */
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MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const pcie_pads[] = {
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/* W_DISABLE# */
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MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
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/* PERST# */
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MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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int dram_init(void)
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{
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gd->ram_size = 2048ul * 1024 * 1024;
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return 0;
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}
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static void setup_iomux_enet(void)
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{
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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/* Reset AR8035 PHY */
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gpio_request(IMX_GPIO_NR(1, 25), "ETH_PHY_RESET");
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gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
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udelay(500);
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gpio_set_value(IMX_GPIO_NR(1, 25), 1);
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}
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static void setup_pcie(void)
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{
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imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
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}
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
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}
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#ifdef CONFIG_FSL_ESDHC_IMX
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/* set environment device to boot device when booting from SD */
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int board_mmc_get_env_dev(int devno)
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{
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return devno - 1;
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}
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int board_mmc_get_env_part(int devno)
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{
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return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
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}
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#endif /* CONFIG_FSL_ESDHC_IMX */
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#ifdef CONFIG_VIDEO_IPUV3
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static void do_enable_hdmi(struct display_info_t const *dev)
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{
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imx_enable_hdmi_phy();
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}
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struct display_info_t const displays[] = {{
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_hdmi,
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.enable = do_enable_hdmi,
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.mode = {
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.name = "HDMI",
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/* 1024x768@60Hz (VESA)*/
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15384,
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.left_margin = 160,
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.right_margin = 24,
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.upper_margin = 29,
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.lower_margin = 3,
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.hsync_len = 136,
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.vsync_len = 6,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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} } };
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size_t display_count = ARRAY_SIZE(displays);
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static void setup_display(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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int reg;
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s32 timeout = 100000;
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enable_ipu_clock();
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imx_setup_hdmi();
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/* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
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reg = readl(&ccm->analog_pll_video);
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reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
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writel(reg, &ccm->analog_pll_video);
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reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
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reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
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reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
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reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
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writel(reg, &ccm->analog_pll_video);
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writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
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writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
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reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
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writel(reg, &ccm->analog_pll_video);
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while (timeout--)
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if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
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break;
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if (timeout < 0)
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printf("Warning: video pll lock timeout!\n");
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reg = readl(&ccm->analog_pll_video);
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reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
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reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
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writel(reg, &ccm->analog_pll_video);
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/* gate ipu1_di0_clk */
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reg = readl(&ccm->CCGR3);
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reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
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writel(reg, &ccm->CCGR3);
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/* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
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reg = readl(&ccm->chsccdr);
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reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
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MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
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MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
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reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
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(6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
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(0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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writel(reg, &ccm->chsccdr);
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/* enable ipu1_di0_clk */
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reg = readl(&ccm->CCGR3);
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reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
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writel(reg, &ccm->CCGR3);
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}
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#endif /* CONFIG_VIDEO_IPUV3 */
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static int ar8035_phy_fixup(struct phy_device *phydev)
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{
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unsigned short val;
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/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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val &= 0xffe3;
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val |= 0x18;
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
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/* introduce tx clock delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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val |= 0x0100;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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ar8035_phy_fixup(phydev);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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setup_iomux_enet();
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setup_pcie();
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return cpu_eth_init(bis);
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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#ifdef CONFIG_CMD_BMODE
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static const struct boot_mode board_boot_modes[] = {
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/* 4 bit bus width */
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{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
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{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
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/* 8 bit bus width */
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{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
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{NULL, 0},
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};
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#endif
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_VIDEO_IPUV3
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setup_display();
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#endif
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#ifdef CONFIG_CMD_BMODE
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add_board_boot_modes(board_boot_modes);
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#endif
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return 0;
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}
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