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https://github.com/brain-hackers/u-boot-brain
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21ff7344d1
Convert cache flush to use dm cpu data.
The original cache flush functions are written in assembly
and use CONFIG_SYS_{I,D}CACHE_SIZE... macros. It is difficult
to convert to use cache configuration in dm cpu data which is
extracted from device tree.
The cacheflush.c of Linux nios2 arch uses cpuinfo structure,
which is very close to our dm cpu data. So we copy and modify
it to arch/nios2/lib/cache.c to replace the old cache.S.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
121 lines
2.6 KiB
C
121 lines
2.6 KiB
C
/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/cache.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_DISPLAY_CPUINFO
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int print_cpuinfo(void)
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{
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printf("CPU: Nios-II\n");
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return 0;
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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disable_interrupts();
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/* indirect call to go beyond 256MB limitation of toolchain */
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nios2_callr(gd->arch.reset_addr);
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return 0;
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}
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int arch_cpu_init_dm(void)
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{
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struct udevice *dev;
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int ret;
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ret = uclass_first_device(UCLASS_CPU, &dev);
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if (ret)
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return ret;
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if (!dev)
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return -ENODEV;
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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static int altera_nios2_get_desc(struct udevice *dev, char *buf, int size)
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{
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const char *cpu_name = "Nios-II";
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if (size < strlen(cpu_name))
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return -ENOSPC;
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strcpy(buf, cpu_name);
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return 0;
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}
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static int altera_nios2_get_info(struct udevice *dev, struct cpu_info *info)
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{
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info->cpu_freq = gd->cpu_clk;
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info->features = (1 << CPU_FEAT_L1_CACHE) |
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(gd->arch.has_mmu ? (1 << CPU_FEAT_MMU) : 0);
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return 0;
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}
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static int altera_nios2_get_count(struct udevice *dev)
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{
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return 1;
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}
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static int altera_nios2_probe(struct udevice *dev)
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{
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const void *blob = gd->fdt_blob;
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int node = dev->of_offset;
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gd->cpu_clk = fdtdec_get_int(blob, node,
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"clock-frequency", 0);
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gd->arch.dcache_line_size = fdtdec_get_int(blob, node,
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"dcache-line-size", 0);
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gd->arch.icache_line_size = fdtdec_get_int(blob, node,
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"icache-line-size", 0);
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gd->arch.dcache_size = fdtdec_get_int(blob, node,
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"dcache-size", 0);
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gd->arch.icache_size = fdtdec_get_int(blob, node,
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"icache-size", 0);
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gd->arch.reset_addr = fdtdec_get_int(blob, node,
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"altr,reset-addr", 0);
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gd->arch.exception_addr = fdtdec_get_int(blob, node,
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"altr,exception-addr", 0);
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gd->arch.has_initda = fdtdec_get_int(blob, node,
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"altr,has-initda", 0);
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gd->arch.has_mmu = fdtdec_get_int(blob, node,
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"altr,has-mmu", 0);
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gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x8000000;
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return 0;
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}
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static const struct cpu_ops altera_nios2_ops = {
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.get_desc = altera_nios2_get_desc,
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.get_info = altera_nios2_get_info,
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.get_count = altera_nios2_get_count,
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};
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static const struct udevice_id altera_nios2_ids[] = {
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{ .compatible = "altr,nios2-1.0" },
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{ .compatible = "altr,nios2-1.1" },
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{ }
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};
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U_BOOT_DRIVER(altera_nios2) = {
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.name = "altera_nios2",
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.id = UCLASS_CPU,
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.of_match = altera_nios2_ids,
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.probe = altera_nios2_probe,
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.ops = &altera_nios2_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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