mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-05 11:00:43 +09:00
0c84358cb2
At present exynos_fimd.c is the controller and exynos_fb.c is the U-Boot LCD interface. With driver model we want these in one file, so join them in preparation. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
687 lines
17 KiB
C
687 lines
17 KiB
C
/*
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* Copyright (C) 2012 Samsung Electronics
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*
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* Author: InKi Dae <inki.dae@samsung.com>
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* Author: Donghwa Lee <dh09.lee@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <div64.h>
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#include <lcd.h>
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#include <fdtdec.h>
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#include <libfdt.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/mipi_dsim.h>
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#include <asm/arch/dp_info.h>
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#include <asm/arch/system.h>
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#include <asm/gpio.h>
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#include <asm-generic/errno.h>
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#include "exynos_fb.h"
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DECLARE_GLOBAL_DATA_PTR;
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struct vidinfo panel_info = {
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/*
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* Insert a value here so that we don't end up in the BSS
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* Reference: drivers/video/tegra.c
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*/
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.vl_col = -1,
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};
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static void exynos_fimd_set_dualrgb(struct vidinfo *pvid, unsigned int enabled)
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{
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
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unsigned int cfg = 0;
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if (enabled) {
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cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
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EXYNOS_DUALRGB_VDEN_EN_ENABLE;
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/* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
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cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) |
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EXYNOS_DUALRGB_MAIN_CNT(0);
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}
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writel(cfg, &fimd_ctrl->dualrgb);
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}
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static void exynos_fimd_set_dp_clkcon(struct vidinfo *pvid,
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unsigned int enabled)
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{
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
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unsigned int cfg = 0;
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if (enabled)
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cfg = EXYNOS_DP_CLK_ENABLE;
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writel(cfg, &fimd_ctrl->dp_mie_clkcon);
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}
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static void exynos_fimd_set_par(struct vidinfo *pvid, unsigned int win_id)
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{
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
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unsigned int cfg = 0;
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/* set window control */
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cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
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EXYNOS_WINCON(win_id));
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cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
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EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
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EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
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EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
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/* DATAPATH is DMA */
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cfg |= EXYNOS_WINCON_DATAPATH_DMA;
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cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
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/* dma burst is 16 */
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cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
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switch (pvid->vl_bpix) {
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case 4:
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cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
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break;
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default:
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cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
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break;
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}
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writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
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EXYNOS_WINCON(win_id));
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/* set window position to x=0, y=0*/
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cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
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writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a +
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EXYNOS_VIDOSD(win_id));
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cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
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EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1) |
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EXYNOS_VIDOSD_RIGHT_X_E(1) |
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EXYNOS_VIDOSD_BOTTOM_Y_E(0);
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writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b +
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EXYNOS_VIDOSD(win_id));
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/* set window size for window0*/
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cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
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writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c +
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EXYNOS_VIDOSD(win_id));
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}
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static void exynos_fimd_set_buffer_address(struct vidinfo *pvid,
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unsigned int win_id,
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ulong lcd_base_addr)
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{
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
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unsigned long start_addr, end_addr;
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start_addr = lcd_base_addr;
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end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
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pvid->vl_row);
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writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 +
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EXYNOS_BUFFER_OFFSET(win_id));
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writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 +
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EXYNOS_BUFFER_OFFSET(win_id));
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}
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static void exynos_fimd_set_clock(struct vidinfo *pvid)
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{
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
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unsigned int cfg = 0, div = 0, remainder, remainder_div;
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unsigned long pixel_clock;
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unsigned long long src_clock;
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if (pvid->dual_lcd_enabled) {
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pixel_clock = pvid->vl_freq *
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(pvid->vl_hspw + pvid->vl_hfpd +
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pvid->vl_hbpd + pvid->vl_col / 2) *
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(pvid->vl_vspw + pvid->vl_vfpd +
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pvid->vl_vbpd + pvid->vl_row);
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} else if (pvid->interface_mode == FIMD_CPU_INTERFACE) {
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pixel_clock = pvid->vl_freq *
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pvid->vl_width * pvid->vl_height *
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(pvid->cs_setup + pvid->wr_setup +
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pvid->wr_act + pvid->wr_hold + 1);
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} else {
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pixel_clock = pvid->vl_freq *
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(pvid->vl_hspw + pvid->vl_hfpd +
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pvid->vl_hbpd + pvid->vl_col) *
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(pvid->vl_vspw + pvid->vl_vfpd +
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pvid->vl_vbpd + pvid->vl_row);
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}
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cfg = readl(&fimd_ctrl->vidcon0);
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cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
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EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
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EXYNOS_VIDCON0_CLKDIR_MASK);
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cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
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EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
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src_clock = (unsigned long long) get_lcd_clk();
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/* get quotient and remainder. */
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remainder = do_div(src_clock, pixel_clock);
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div = src_clock;
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remainder *= 10;
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remainder_div = remainder / pixel_clock;
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/* round about one places of decimals. */
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if (remainder_div >= 5)
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div++;
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/* in case of dual lcd mode. */
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if (pvid->dual_lcd_enabled)
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div--;
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cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
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writel(cfg, &fimd_ctrl->vidcon0);
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}
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void exynos_set_trigger(struct vidinfo *pvid)
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{
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
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unsigned int cfg = 0;
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cfg = readl(&fimd_ctrl->trigcon);
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cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
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writel(cfg, &fimd_ctrl->trigcon);
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}
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int exynos_is_i80_frame_done(struct vidinfo *pvid)
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{
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
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unsigned int cfg = 0;
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int status;
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cfg = readl(&fimd_ctrl->trigcon);
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/* frame done func is valid only when TRIMODE[0] is set to 1. */
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status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
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EXYNOS_I80STATUS_TRIG_DONE;
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return status;
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}
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static void exynos_fimd_lcd_on(struct vidinfo *pvid)
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{
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
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unsigned int cfg = 0;
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/* display on */
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cfg = readl(&fimd_ctrl->vidcon0);
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cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
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writel(cfg, &fimd_ctrl->vidcon0);
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}
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static void exynos_fimd_window_on(struct vidinfo *pvid, unsigned int win_id)
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{
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
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unsigned int cfg = 0;
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/* enable window */
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cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
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EXYNOS_WINCON(win_id));
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cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
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writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
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EXYNOS_WINCON(win_id));
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cfg = readl(&fimd_ctrl->winshmap);
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cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
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writel(cfg, &fimd_ctrl->winshmap);
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}
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void exynos_fimd_lcd_off(struct vidinfo *pvid)
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{
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
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unsigned int cfg = 0;
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cfg = readl(&fimd_ctrl->vidcon0);
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cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
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writel(cfg, &fimd_ctrl->vidcon0);
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}
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void exynos_fimd_window_off(struct vidinfo *pvid, unsigned int win_id)
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{
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
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unsigned int cfg = 0;
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cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
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EXYNOS_WINCON(win_id));
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cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
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writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
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EXYNOS_WINCON(win_id));
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cfg = readl(&fimd_ctrl->winshmap);
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cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
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writel(cfg, &fimd_ctrl->winshmap);
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}
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/*
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* The reset value for FIMD SYSMMU register MMU_CTRL is 3
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* on Exynos5420 and newer versions.
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* This means FIMD SYSMMU is on by default on Exynos5420
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* and newer versions.
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* Since in u-boot we don't use SYSMMU, we should disable
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* those FIMD SYSMMU.
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* Note that there are 2 SYSMMU for FIMD: m0 and m1.
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* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
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* We disable both of them here.
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*/
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void exynos_fimd_disable_sysmmu(void)
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{
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u32 *sysmmufimd;
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unsigned int node;
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int node_list[2];
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int count;
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int i;
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count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
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COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
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for (i = 0; i < count; i++) {
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node = node_list[i];
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if (node <= 0) {
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debug("Can't get device node for fimd sysmmu\n");
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return;
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}
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sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
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if (!sysmmufimd) {
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debug("Can't get base address for sysmmu fimdm0");
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return;
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}
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writel(0x0, sysmmufimd);
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}
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}
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void exynos_fimd_lcd_init(struct vidinfo *pvid, ulong lcd_base_address)
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{
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struct exynos_fb *fimd_ctrl;
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unsigned int cfg = 0, rgb_mode;
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unsigned int offset;
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unsigned int node;
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node = fdtdec_next_compatible(gd->fdt_blob,
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0, COMPAT_SAMSUNG_EXYNOS_FIMD);
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if (node <= 0)
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debug("exynos_fb: Can't get device node for fimd\n");
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fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob, node,
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"reg");
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if (fimd_ctrl == NULL)
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debug("Can't get the FIMD base address\n");
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pvid->fimd_ctrl = fimd_ctrl;
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if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
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exynos_fimd_disable_sysmmu();
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offset = exynos_fimd_get_base_offset();
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rgb_mode = pvid->rgb_mode;
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if (pvid->interface_mode == FIMD_RGB_INTERFACE) {
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cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
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writel(cfg, &fimd_ctrl->vidcon0);
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cfg = readl(&fimd_ctrl->vidcon2);
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cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
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EXYNOS_VIDCON2_TVFORMATSEL_MASK |
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EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
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cfg |= EXYNOS_VIDCON2_WB_DISABLE;
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writel(cfg, &fimd_ctrl->vidcon2);
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/* set polarity */
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cfg = 0;
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if (!pvid->vl_clkp)
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cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
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if (!pvid->vl_hsp)
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cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
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if (!pvid->vl_vsp)
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cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
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if (!pvid->vl_dp)
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cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
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writel(cfg, (unsigned int)&fimd_ctrl->vidcon1 + offset);
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/* set timing */
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cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
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cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
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cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1);
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writel(cfg, (unsigned int)&fimd_ctrl->vidtcon0 + offset);
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cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
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cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
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cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1);
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writel(cfg, (unsigned int)&fimd_ctrl->vidtcon1 + offset);
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/* set lcd size */
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cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1) |
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EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1) |
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EXYNOS_VIDTCON2_HOZVAL_E(pvid->vl_col - 1) |
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EXYNOS_VIDTCON2_LINEVAL_E(pvid->vl_row - 1);
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writel(cfg, (unsigned int)&fimd_ctrl->vidtcon2 + offset);
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}
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/* set display mode */
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cfg = readl(&fimd_ctrl->vidcon0);
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cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
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cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
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writel(cfg, &fimd_ctrl->vidcon0);
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/* set par */
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exynos_fimd_set_par(pvid, pvid->win_id);
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/* set memory address */
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exynos_fimd_set_buffer_address(pvid, pvid->win_id, lcd_base_address);
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/* set buffer size */
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cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col *
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NBITS(pvid->vl_bpix) / 8) |
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EXYNOS_VIDADDR_PAGEWIDTH_E(pvid->vl_col *
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NBITS(pvid->vl_bpix) / 8) |
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EXYNOS_VIDADDR_OFFSIZE(0) |
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EXYNOS_VIDADDR_OFFSIZE_E(0);
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writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 +
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EXYNOS_BUFFER_SIZE(pvid->win_id));
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/* set clock */
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exynos_fimd_set_clock(pvid);
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/* set rgb mode to dual lcd. */
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exynos_fimd_set_dualrgb(pvid, pvid->dual_lcd_enabled);
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/* display on */
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exynos_fimd_lcd_on(pvid);
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/* window on */
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exynos_fimd_window_on(pvid, pvid->win_id);
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exynos_fimd_set_dp_clkcon(pvid, pvid->dp_enabled);
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}
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unsigned long exynos_fimd_calc_fbsize(struct vidinfo *pvid)
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{
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return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8);
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}
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ushort *configuration_get_cmap(void)
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{
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#if defined(CONFIG_LCD_LOGO)
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return bmp_logo_palette;
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#else
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return NULL;
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#endif
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}
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static void exynos_lcd_init(struct vidinfo *vid, ulong lcd_base)
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{
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exynos_fimd_lcd_init(vid, lcd_base);
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/* Enable flushing after LCD writes if requested */
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lcd_set_flush_dcache(1);
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}
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__weak void exynos_cfg_lcd_gpio(void)
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{
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}
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__weak void exynos_backlight_on(unsigned int onoff)
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{
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}
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__weak void exynos_reset_lcd(void)
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{
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}
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__weak void exynos_lcd_power_on(void)
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{
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}
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__weak void exynos_cfg_ldo(void)
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{
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}
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__weak void exynos_enable_ldo(unsigned int onoff)
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{
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}
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__weak void exynos_backlight_reset(void)
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{
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}
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__weak int exynos_lcd_misc_init(struct vidinfo *vid)
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{
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return 0;
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}
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static void lcd_panel_on(struct vidinfo *vid)
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{
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struct gpio_desc pwm_out_gpio;
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struct gpio_desc bl_en_gpio;
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unsigned int node;
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udelay(vid->init_delay);
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exynos_backlight_reset();
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exynos_cfg_lcd_gpio();
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exynos_lcd_power_on();
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udelay(vid->power_on_delay);
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if (vid->dp_enabled)
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exynos_init_dp();
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exynos_reset_lcd();
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udelay(vid->reset_delay);
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exynos_backlight_on(1);
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node = fdtdec_next_compatible(gd->fdt_blob, 0,
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COMPAT_SAMSUNG_EXYNOS_FIMD);
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if (node <= 0) {
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debug("FIMD: Can't get device node for FIMD\n");
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return;
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}
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gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio",
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0, &pwm_out_gpio,
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GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0,
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&bl_en_gpio,
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GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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exynos_cfg_ldo();
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exynos_enable_ldo(1);
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if (vid->mipi_enabled)
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exynos_mipi_dsi_init(panel_info.dsim_platform_data_dt);
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}
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int exynos_lcd_early_init(const void *blob)
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{
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unsigned int node;
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node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
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if (node <= 0) {
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debug("exynos_fb: Can't get device node for fimd\n");
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return -ENODEV;
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}
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panel_info.vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0);
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if (panel_info.vl_col == 0) {
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debug("Can't get XRES\n");
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return -ENXIO;
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}
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panel_info.vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0);
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if (panel_info.vl_row == 0) {
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debug("Can't get YRES\n");
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return -ENXIO;
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}
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panel_info.vl_width = fdtdec_get_int(blob, node,
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"samsung,vl-width", 0);
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panel_info.vl_height = fdtdec_get_int(blob, node,
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"samsung,vl-height", 0);
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panel_info.vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0);
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if (panel_info.vl_freq == 0) {
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debug("Can't get refresh rate\n");
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return -ENXIO;
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}
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if (fdtdec_get_bool(blob, node, "samsung,vl-clkp"))
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panel_info.vl_clkp = CONFIG_SYS_LOW;
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if (fdtdec_get_bool(blob, node, "samsung,vl-oep"))
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panel_info.vl_oep = CONFIG_SYS_LOW;
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if (fdtdec_get_bool(blob, node, "samsung,vl-hsp"))
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panel_info.vl_hsp = CONFIG_SYS_LOW;
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if (fdtdec_get_bool(blob, node, "samsung,vl-vsp"))
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panel_info.vl_vsp = CONFIG_SYS_LOW;
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if (fdtdec_get_bool(blob, node, "samsung,vl-dp"))
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panel_info.vl_dp = CONFIG_SYS_LOW;
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panel_info.vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0);
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if (panel_info.vl_bpix == 0) {
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debug("Can't get bits per pixel\n");
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return -ENXIO;
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}
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panel_info.vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0);
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if (panel_info.vl_hspw == 0) {
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debug("Can't get hsync width\n");
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return -ENXIO;
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}
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panel_info.vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0);
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if (panel_info.vl_hfpd == 0) {
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debug("Can't get right margin\n");
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return -ENXIO;
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}
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panel_info.vl_hbpd = (u_char)fdtdec_get_int(blob, node,
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"samsung,vl-hbpd", 0);
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if (panel_info.vl_hbpd == 0) {
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debug("Can't get left margin\n");
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return -ENXIO;
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}
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panel_info.vl_vspw = (u_char)fdtdec_get_int(blob, node,
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"samsung,vl-vspw", 0);
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if (panel_info.vl_vspw == 0) {
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debug("Can't get vsync width\n");
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return -ENXIO;
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}
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panel_info.vl_vfpd = fdtdec_get_int(blob, node,
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"samsung,vl-vfpd", 0);
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if (panel_info.vl_vfpd == 0) {
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debug("Can't get lower margin\n");
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return -ENXIO;
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}
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panel_info.vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0);
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if (panel_info.vl_vbpd == 0) {
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debug("Can't get upper margin\n");
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return -ENXIO;
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}
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panel_info.vl_cmd_allow_len = fdtdec_get_int(blob, node,
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"samsung,vl-cmd-allow-len", 0);
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panel_info.win_id = fdtdec_get_int(blob, node, "samsung,winid", 0);
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panel_info.init_delay = fdtdec_get_int(blob, node,
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"samsung,init-delay", 0);
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panel_info.power_on_delay = fdtdec_get_int(blob, node,
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"samsung,power-on-delay", 0);
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panel_info.reset_delay = fdtdec_get_int(blob, node,
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"samsung,reset-delay", 0);
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panel_info.interface_mode = fdtdec_get_int(blob, node,
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"samsung,interface-mode", 0);
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panel_info.mipi_enabled = fdtdec_get_int(blob, node,
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"samsung,mipi-enabled", 0);
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panel_info.dp_enabled = fdtdec_get_int(blob, node,
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"samsung,dp-enabled", 0);
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panel_info.cs_setup = fdtdec_get_int(blob, node,
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"samsung,cs-setup", 0);
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panel_info.wr_setup = fdtdec_get_int(blob, node,
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"samsung,wr-setup", 0);
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panel_info.wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0);
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panel_info.wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0);
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panel_info.logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0);
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if (panel_info.logo_on) {
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panel_info.logo_width = fdtdec_get_int(blob, node,
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"samsung,logo-width", 0);
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panel_info.logo_height = fdtdec_get_int(blob, node,
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"samsung,logo-height", 0);
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panel_info.logo_addr = fdtdec_get_int(blob, node,
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"samsung,logo-addr", 0);
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}
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panel_info.rgb_mode = fdtdec_get_int(blob, node,
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"samsung,rgb-mode", 0);
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panel_info.pclk_name = fdtdec_get_int(blob, node,
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"samsung,pclk-name", 0);
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panel_info.sclk_div = fdtdec_get_int(blob, node,
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"samsung,sclk-div", 0);
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panel_info.dual_lcd_enabled = fdtdec_get_int(blob, node,
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"samsung,dual-lcd-enabled", 0);
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return 0;
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}
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void lcd_ctrl_init(void *lcdbase)
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{
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set_system_display_ctrl();
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set_lcd_clk();
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#ifdef CONFIG_EXYNOS_MIPI_DSIM
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exynos_init_dsim_platform_data(&panel_info);
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#endif
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exynos_lcd_misc_init(&panel_info);
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exynos_lcd_init(&panel_info, (ulong)lcdbase);
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}
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void lcd_enable(void)
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{
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if (panel_info.logo_on) {
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memset((void *)gd->fb_base, 0,
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panel_info.vl_width * panel_info.vl_height *
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(NBITS(panel_info.vl_bpix) >> 3));
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}
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lcd_panel_on(&panel_info);
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}
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/* dummy function */
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void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
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{
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return;
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}
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