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https://github.com/brain-hackers/u-boot-brain
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![Walter Lozano](/assets/img/avatar_default.png)
When using OF_PLATDATA, the bind process between devices and drivers is performed trying to match compatible string with driver names. However driver names are not strictly defined, and also there are different names used when declaring a driver with U_BOOT_DRIVER, the name of the symbol used in the linker list and the used in the struct driver_info. In order to make things a bit more clear, rename the drivers names. This will also help for further OF_PLATDATA improvements, such as checking for valid driver names. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> Add a fix for sandbox of-platdata to avoid using an invalid ANSI colour: Signed-off-by: Simon Glass <sjg@chromium.org>
962 lines
25 KiB
C
962 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* (C) Copyright 2015 Google, Inc
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* Copyright 2014 Rockchip Inc.
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*
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* Adapted from the very similar rk3288 ddr init.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <errno.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <ram.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/cru_rk3188.h>
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#include <asm/arch-rockchip/ddr_rk3188.h>
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#include <asm/arch-rockchip/grf_rk3188.h>
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#include <asm/arch-rockchip/pmu_rk3188.h>
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#include <asm/arch-rockchip/sdram.h>
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#include <asm/arch-rockchip/sdram_rk3288.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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struct chan_info {
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struct rk3288_ddr_pctl *pctl;
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struct rk3288_ddr_publ *publ;
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struct rk3188_msch *msch;
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};
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struct dram_info {
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struct chan_info chan[1];
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struct ram_info info;
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struct clk ddr_clk;
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struct rk3188_cru *cru;
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struct rk3188_grf *grf;
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struct rk3188_sgrf *sgrf;
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struct rk3188_pmu *pmu;
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};
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struct rk3188_sdram_params {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rk3188_dmc of_plat;
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#endif
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struct rk3288_sdram_channel ch[2];
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struct rk3288_sdram_pctl_timing pctl_timing;
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struct rk3288_sdram_phy_timing phy_timing;
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struct rk3288_base_params base;
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int num_channels;
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struct regmap *map;
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};
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const int ddrconf_table[] = {
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/*
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* [5:4] row(13+n)
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* [1:0] col(9+n), assume bw=2
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* row col,bw
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*/
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0,
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((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
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((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
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((0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
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((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
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((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
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((0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
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((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
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((0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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};
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#define TEST_PATTEN 0x5aa5f00f
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#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4)
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#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
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#ifdef CONFIG_SPL_BUILD
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static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
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{
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int i;
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for (i = 0; i < n / sizeof(u32); i++) {
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writel(*src, dest);
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src++;
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dest++;
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}
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}
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static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy)
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{
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u32 phy_ctl_srstn_shift = 13;
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u32 ctl_psrstn_shift = 11;
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u32 ctl_srstn_shift = 10;
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u32 phy_psrstn_shift = 9;
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u32 phy_srstn_shift = 8;
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rk_clrsetreg(&cru->cru_softrst_con[5],
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1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
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1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
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1 << phy_srstn_shift,
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phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
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ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
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phy << phy_srstn_shift);
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}
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static void ddr_phy_ctl_reset(struct rk3188_cru *cru, u32 ch, u32 n)
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{
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u32 phy_ctl_srstn_shift = 13;
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rk_clrsetreg(&cru->cru_softrst_con[5],
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1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
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}
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static void phy_pctrl_reset(struct rk3188_cru *cru,
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struct rk3288_ddr_publ *publ,
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int channel)
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{
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int i;
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ddr_reset(cru, channel, 1, 1);
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udelay(1);
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clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
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for (i = 0; i < 4; i++)
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clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
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udelay(10);
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setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
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for (i = 0; i < 4; i++)
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setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
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udelay(10);
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ddr_reset(cru, channel, 1, 0);
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udelay(10);
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ddr_reset(cru, channel, 0, 0);
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udelay(10);
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}
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static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ,
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u32 freq)
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{
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int i;
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if (freq <= 250000000) {
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if (freq <= 150000000)
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clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
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else
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setbits_le32(&publ->dllgcr, SBIAS_BYPASS);
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setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
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for (i = 0; i < 4; i++)
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setbits_le32(&publ->datx8[i].dxdllcr,
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DXDLLCR_DLLDIS);
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setbits_le32(&publ->pir, PIR_DLLBYP);
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} else {
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clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
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clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
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for (i = 0; i < 4; i++) {
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clrbits_le32(&publ->datx8[i].dxdllcr,
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DXDLLCR_DLLDIS);
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}
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clrbits_le32(&publ->pir, PIR_DLLBYP);
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}
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}
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static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)
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{
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writel(DFI_INIT_START, &pctl->dfistcfg0);
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writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
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&pctl->dfistcfg1);
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writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
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writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
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&pctl->dfilpcfg0);
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writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);
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writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);
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writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);
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writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);
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writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);
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writel(1, &pctl->dfitphyupdtype0);
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/* cs0 and cs1 write odt enable */
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writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
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&pctl->dfiodtcfg);
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/* odt write length */
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writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
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/* phyupd and ctrlupd disabled */
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writel(0, &pctl->dfiupdcfg);
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}
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static void ddr_set_enable(struct rk3188_grf *grf, uint channel, bool enable)
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{
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uint val = 0;
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if (enable)
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val = 1 << DDR_16BIT_EN_SHIFT;
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rk_clrsetreg(&grf->ddrc_con0, 1 << DDR_16BIT_EN_SHIFT, val);
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}
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static void ddr_set_ddr3_mode(struct rk3188_grf *grf, uint channel,
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bool ddr3_mode)
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{
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uint mask, val;
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mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT;
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val = ddr3_mode << MSCH4_MAINDDR3_SHIFT;
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rk_clrsetreg(&grf->soc_con2, mask, val);
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}
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static void ddr_rank_2_row15en(struct rk3188_grf *grf, bool enable)
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{
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uint mask, val;
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mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT;
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val = enable << RANK_TO_ROW15_EN_SHIFT;
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rk_clrsetreg(&grf->soc_con2, mask, val);
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}
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static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,
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struct rk3188_sdram_params *sdram_params,
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struct rk3188_grf *grf)
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{
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copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
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sizeof(sdram_params->pctl_timing));
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switch (sdram_params->base.dramtype) {
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case DDR3:
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if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
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writel(sdram_params->pctl_timing.tcl - 3,
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&pctl->dfitrddataen);
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} else {
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writel(sdram_params->pctl_timing.tcl - 2,
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&pctl->dfitrddataen);
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}
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writel(sdram_params->pctl_timing.tcwl - 1,
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&pctl->dfitphywrlat);
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writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
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DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
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1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
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&pctl->mcfg);
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ddr_set_ddr3_mode(grf, channel, true);
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ddr_set_enable(grf, channel, true);
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break;
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}
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setbits_le32(&pctl->scfg, 1);
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}
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static void phy_cfg(const struct chan_info *chan, int channel,
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struct rk3188_sdram_params *sdram_params)
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{
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struct rk3288_ddr_publ *publ = chan->publ;
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struct rk3188_msch *msch = chan->msch;
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uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
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u32 dinit2;
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int i;
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dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000);
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/* DDR PHY Timing */
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copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
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sizeof(sdram_params->phy_timing));
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writel(sdram_params->base.noc_timing, &msch->ddrtiming);
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writel(0x3f, &msch->readlatency);
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writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT |
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DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT |
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8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);
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writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT |
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DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT,
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&publ->ptr[1]);
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writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT |
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DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT,
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&publ->ptr[2]);
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switch (sdram_params->base.dramtype) {
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case DDR3:
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clrbits_le32(&publ->pgcr, 0x1f);
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clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
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DDRMD_DDR3 << DDRMD_SHIFT);
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break;
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}
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if (sdram_params->base.odt) {
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/*dynamic RTT enable */
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for (i = 0; i < 4; i++)
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setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
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} else {
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/*dynamic RTT disable */
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for (i = 0; i < 4; i++)
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clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
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}
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}
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static void phy_init(struct rk3288_ddr_publ *publ)
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{
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setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST
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| PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
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udelay(1);
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while ((readl(&publ->pgsr) &
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(PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
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(PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
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;
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}
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static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank,
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u32 cmd, u32 arg)
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{
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writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
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udelay(1);
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while (readl(&pctl->mcmd) & START_CMD)
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;
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}
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static inline void send_command_op(struct rk3288_ddr_pctl *pctl,
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u32 rank, u32 cmd, u32 ma, u32 op)
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{
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send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
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(op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT);
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}
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static void memory_init(struct rk3288_ddr_publ *publ,
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u32 dramtype)
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{
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setbits_le32(&publ->pir,
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(PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
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| PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
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| (dramtype == DDR3 ? PIR_DRAMRST : 0)));
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udelay(1);
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while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
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!= (PGSR_IDONE | PGSR_DLDONE))
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;
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}
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static void move_to_config_state(struct rk3288_ddr_publ *publ,
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struct rk3288_ddr_pctl *pctl)
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{
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unsigned int state;
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while (1) {
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state = readl(&pctl->stat) & PCTL_STAT_MSK;
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switch (state) {
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case LOW_POWER:
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writel(WAKEUP_STATE, &pctl->sctl);
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while ((readl(&pctl->stat) & PCTL_STAT_MSK)
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!= ACCESS)
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;
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/* wait DLL lock */
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while ((readl(&publ->pgsr) & PGSR_DLDONE)
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!= PGSR_DLDONE)
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;
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/*
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* if at low power state,need wakeup first,
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* and then enter the config, so
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* fallthrough
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*/
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case ACCESS:
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/* fallthrough */
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case INIT_MEM:
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writel(CFG_STATE, &pctl->sctl);
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while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
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;
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break;
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case CONFIG:
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return;
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default:
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break;
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}
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}
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}
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static void set_bandwidth_ratio(const struct chan_info *chan, int channel,
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u32 n, struct rk3188_grf *grf)
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{
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struct rk3288_ddr_pctl *pctl = chan->pctl;
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struct rk3288_ddr_publ *publ = chan->publ;
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struct rk3188_msch *msch = chan->msch;
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if (n == 1) {
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setbits_le32(&pctl->ppcfg, 1);
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ddr_set_enable(grf, channel, 1);
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setbits_le32(&msch->ddrtiming, 1 << 31);
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/* Data Byte disable*/
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clrbits_le32(&publ->datx8[2].dxgcr, 1);
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clrbits_le32(&publ->datx8[3].dxgcr, 1);
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/* disable DLL */
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setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
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setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
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} else {
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clrbits_le32(&pctl->ppcfg, 1);
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ddr_set_enable(grf, channel, 0);
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clrbits_le32(&msch->ddrtiming, 1 << 31);
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/* Data Byte enable*/
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setbits_le32(&publ->datx8[2].dxgcr, 1);
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setbits_le32(&publ->datx8[3].dxgcr, 1);
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/* enable DLL */
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clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
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clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
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/* reset DLL */
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clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
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clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
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udelay(10);
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setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
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setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
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}
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setbits_le32(&pctl->dfistcfg0, 1 << 2);
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}
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static int data_training(const struct chan_info *chan, int channel,
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struct rk3188_sdram_params *sdram_params)
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{
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unsigned int j;
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int ret = 0;
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|
u32 rank;
|
|
int i;
|
|
u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
|
|
struct rk3288_ddr_publ *publ = chan->publ;
|
|
struct rk3288_ddr_pctl *pctl = chan->pctl;
|
|
|
|
/* disable auto refresh */
|
|
writel(0, &pctl->trefi);
|
|
|
|
if (sdram_params->base.dramtype != LPDDR3)
|
|
setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
|
|
rank = sdram_params->ch[channel].rank | 1;
|
|
for (j = 0; j < ARRAY_SIZE(step); j++) {
|
|
/*
|
|
* trigger QSTRN and RVTRN
|
|
* clear DTDONE status
|
|
*/
|
|
setbits_le32(&publ->pir, PIR_CLRSR);
|
|
|
|
/* trigger DTT */
|
|
setbits_le32(&publ->pir,
|
|
PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
|
|
PIR_CLRSR);
|
|
udelay(1);
|
|
/* wait echo byte DTDONE */
|
|
while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
|
|
!= rank)
|
|
;
|
|
while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
|
|
!= rank)
|
|
;
|
|
if (!(readl(&pctl->ppcfg) & 1)) {
|
|
while ((readl(&publ->datx8[2].dxgsr[0])
|
|
& rank) != rank)
|
|
;
|
|
while ((readl(&publ->datx8[3].dxgsr[0])
|
|
& rank) != rank)
|
|
;
|
|
}
|
|
if (readl(&publ->pgsr) &
|
|
(PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
|
|
ret = -1;
|
|
break;
|
|
}
|
|
}
|
|
/* send some auto refresh to complement the lost while DTT */
|
|
for (i = 0; i < (rank > 1 ? 8 : 4); i++)
|
|
send_command(pctl, rank, REF_CMD, 0);
|
|
|
|
if (sdram_params->base.dramtype != LPDDR3)
|
|
clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
|
|
|
|
/* resume auto refresh */
|
|
writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void move_to_access_state(const struct chan_info *chan)
|
|
{
|
|
struct rk3288_ddr_publ *publ = chan->publ;
|
|
struct rk3288_ddr_pctl *pctl = chan->pctl;
|
|
unsigned int state;
|
|
|
|
while (1) {
|
|
state = readl(&pctl->stat) & PCTL_STAT_MSK;
|
|
|
|
switch (state) {
|
|
case LOW_POWER:
|
|
if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
|
|
LP_TRIG_MASK) == 1)
|
|
return;
|
|
|
|
writel(WAKEUP_STATE, &pctl->sctl);
|
|
while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
|
|
;
|
|
/* wait DLL lock */
|
|
while ((readl(&publ->pgsr) & PGSR_DLDONE)
|
|
!= PGSR_DLDONE)
|
|
;
|
|
break;
|
|
case INIT_MEM:
|
|
writel(CFG_STATE, &pctl->sctl);
|
|
while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
|
|
;
|
|
/* fallthrough */
|
|
case CONFIG:
|
|
writel(GO_STATE, &pctl->sctl);
|
|
while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
|
|
;
|
|
break;
|
|
case ACCESS:
|
|
return;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
|
|
struct rk3188_sdram_params *sdram_params)
|
|
{
|
|
struct rk3288_ddr_publ *publ = chan->publ;
|
|
|
|
if (sdram_params->ch[chnum].bk == 3)
|
|
clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,
|
|
1 << PDQ_SHIFT);
|
|
else
|
|
clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);
|
|
|
|
writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
|
|
}
|
|
|
|
static void dram_all_config(const struct dram_info *dram,
|
|
struct rk3188_sdram_params *sdram_params)
|
|
{
|
|
unsigned int chan;
|
|
u32 sys_reg = 0;
|
|
|
|
sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
|
|
sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
|
|
for (chan = 0; chan < sdram_params->num_channels; chan++) {
|
|
const struct rk3288_sdram_channel *info =
|
|
&sdram_params->ch[chan];
|
|
|
|
sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
|
|
sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
|
|
sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
|
|
sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
|
|
sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
|
|
sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
|
|
sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
|
|
sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
|
|
sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
|
|
|
|
dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
|
|
}
|
|
if (sdram_params->ch[0].rank == 2)
|
|
ddr_rank_2_row15en(dram->grf, 0);
|
|
else
|
|
ddr_rank_2_row15en(dram->grf, 1);
|
|
|
|
writel(sys_reg, &dram->pmu->sys_reg[2]);
|
|
}
|
|
|
|
static int sdram_rank_bw_detect(struct dram_info *dram, int channel,
|
|
struct rk3188_sdram_params *sdram_params)
|
|
{
|
|
int reg;
|
|
int need_trainig = 0;
|
|
const struct chan_info *chan = &dram->chan[channel];
|
|
struct rk3288_ddr_publ *publ = chan->publ;
|
|
|
|
ddr_rank_2_row15en(dram->grf, 0);
|
|
|
|
if (data_training(chan, channel, sdram_params) < 0) {
|
|
printf("first data training fail!\n");
|
|
reg = readl(&publ->datx8[0].dxgsr[0]);
|
|
/* Check the result for rank 0 */
|
|
if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
|
|
printf("data training fail!\n");
|
|
return -EIO;
|
|
}
|
|
|
|
/* Check the result for rank 1 */
|
|
if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
|
|
sdram_params->ch[channel].rank = 1;
|
|
clrsetbits_le32(&publ->pgcr, 0xF << 18,
|
|
sdram_params->ch[channel].rank << 18);
|
|
need_trainig = 1;
|
|
}
|
|
reg = readl(&publ->datx8[2].dxgsr[0]);
|
|
if (reg & (1 << 4)) {
|
|
sdram_params->ch[channel].bw = 1;
|
|
set_bandwidth_ratio(chan, channel,
|
|
sdram_params->ch[channel].bw,
|
|
dram->grf);
|
|
need_trainig = 1;
|
|
}
|
|
}
|
|
/* Assume the Die bit width are the same with the chip bit width */
|
|
sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
|
|
|
|
if (need_trainig &&
|
|
(data_training(chan, channel, sdram_params) < 0)) {
|
|
if (sdram_params->base.dramtype == LPDDR3) {
|
|
ddr_phy_ctl_reset(dram->cru, channel, 1);
|
|
udelay(10);
|
|
ddr_phy_ctl_reset(dram->cru, channel, 0);
|
|
udelay(10);
|
|
}
|
|
printf("2nd data training failed!");
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Detect ram columns and rows.
|
|
* @dram: dram info struct
|
|
* @channel: channel number to handle
|
|
* @sdram_params: sdram parameters, function will fill in col and row values
|
|
*
|
|
* Returns 0 or negative on error.
|
|
*/
|
|
static int sdram_col_row_detect(struct dram_info *dram, int channel,
|
|
struct rk3188_sdram_params *sdram_params)
|
|
{
|
|
int row, col;
|
|
unsigned int addr;
|
|
const struct chan_info *chan = &dram->chan[channel];
|
|
struct rk3288_ddr_pctl *pctl = chan->pctl;
|
|
struct rk3288_ddr_publ *publ = chan->publ;
|
|
int ret = 0;
|
|
|
|
/* Detect col */
|
|
for (col = 11; col >= 9; col--) {
|
|
writel(0, CONFIG_SYS_SDRAM_BASE);
|
|
addr = CONFIG_SYS_SDRAM_BASE +
|
|
(1 << (col + sdram_params->ch[channel].bw - 1));
|
|
writel(TEST_PATTEN, addr);
|
|
if ((readl(addr) == TEST_PATTEN) &&
|
|
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
|
|
break;
|
|
}
|
|
if (col == 8) {
|
|
printf("Col detect error\n");
|
|
ret = -EINVAL;
|
|
goto out;
|
|
} else {
|
|
sdram_params->ch[channel].col = col;
|
|
}
|
|
|
|
ddr_rank_2_row15en(dram->grf, 1);
|
|
move_to_config_state(publ, pctl);
|
|
writel(1, &chan->msch->ddrconf);
|
|
move_to_access_state(chan);
|
|
/* Detect row, max 15,min13 in rk3188*/
|
|
for (row = 16; row >= 13; row--) {
|
|
writel(0, CONFIG_SYS_SDRAM_BASE);
|
|
addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
|
|
writel(TEST_PATTEN, addr);
|
|
if ((readl(addr) == TEST_PATTEN) &&
|
|
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
|
|
break;
|
|
}
|
|
if (row == 12) {
|
|
printf("Row detect error\n");
|
|
ret = -EINVAL;
|
|
} else {
|
|
sdram_params->ch[channel].cs1_row = row;
|
|
sdram_params->ch[channel].row_3_4 = 0;
|
|
debug("chn %d col %d, row %d\n", channel, col, row);
|
|
sdram_params->ch[channel].cs0_row = row;
|
|
}
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int sdram_get_niu_config(struct rk3188_sdram_params *sdram_params)
|
|
{
|
|
int i, tmp, size, row, ret = 0;
|
|
|
|
row = sdram_params->ch[0].cs0_row;
|
|
/*
|
|
* RK3188 share the rank and row bit15, we use same ddr config for 15bit
|
|
* and 16bit row
|
|
*/
|
|
if (row == 16)
|
|
row = 15;
|
|
tmp = sdram_params->ch[0].col - 9;
|
|
tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
|
|
tmp |= ((row - 13) << 4);
|
|
size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]);
|
|
for (i = 0; i < size; i++)
|
|
if (tmp == ddrconf_table[i])
|
|
break;
|
|
if (i >= size) {
|
|
printf("niu config not found\n");
|
|
ret = -EINVAL;
|
|
} else {
|
|
debug("niu config %d\n", i);
|
|
sdram_params->base.ddrconfig = i;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sdram_init(struct dram_info *dram,
|
|
struct rk3188_sdram_params *sdram_params)
|
|
{
|
|
int channel;
|
|
int zqcr;
|
|
int ret;
|
|
|
|
if ((sdram_params->base.dramtype == DDR3 &&
|
|
sdram_params->base.ddr_freq > 800000000)) {
|
|
printf("SDRAM frequency is too high!");
|
|
return -E2BIG;
|
|
}
|
|
|
|
ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
|
|
if (ret) {
|
|
printf("Could not set DDR clock\n");
|
|
return ret;
|
|
}
|
|
|
|
for (channel = 0; channel < 1; channel++) {
|
|
const struct chan_info *chan = &dram->chan[channel];
|
|
struct rk3288_ddr_pctl *pctl = chan->pctl;
|
|
struct rk3288_ddr_publ *publ = chan->publ;
|
|
|
|
phy_pctrl_reset(dram->cru, publ, channel);
|
|
phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
|
|
|
|
dfi_cfg(pctl, sdram_params->base.dramtype);
|
|
|
|
pctl_cfg(channel, pctl, sdram_params, dram->grf);
|
|
|
|
phy_cfg(chan, channel, sdram_params);
|
|
|
|
phy_init(publ);
|
|
|
|
writel(POWER_UP_START, &pctl->powctl);
|
|
while (!(readl(&pctl->powstat) & POWER_UP_DONE))
|
|
;
|
|
|
|
memory_init(publ, sdram_params->base.dramtype);
|
|
move_to_config_state(publ, pctl);
|
|
|
|
/* Using 32bit bus width for detect */
|
|
sdram_params->ch[channel].bw = 2;
|
|
set_bandwidth_ratio(chan, channel,
|
|
sdram_params->ch[channel].bw, dram->grf);
|
|
/*
|
|
* set cs, using n=3 for detect
|
|
* CS0, n=1
|
|
* CS1, n=2
|
|
* CS0 & CS1, n = 3
|
|
*/
|
|
sdram_params->ch[channel].rank = 2,
|
|
clrsetbits_le32(&publ->pgcr, 0xF << 18,
|
|
(sdram_params->ch[channel].rank | 1) << 18);
|
|
|
|
/* DS=40ohm,ODT=155ohm */
|
|
zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
|
|
2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
|
|
0x19 << PD_OUTPUT_SHIFT;
|
|
writel(zqcr, &publ->zq1cr[0]);
|
|
writel(zqcr, &publ->zq0cr[0]);
|
|
|
|
/* Detect the rank and bit-width with data-training */
|
|
writel(1, &chan->msch->ddrconf);
|
|
sdram_rank_bw_detect(dram, channel, sdram_params);
|
|
|
|
if (sdram_params->base.dramtype == LPDDR3) {
|
|
u32 i;
|
|
writel(0, &pctl->mrrcfg0);
|
|
for (i = 0; i < 17; i++)
|
|
send_command_op(pctl, 1, MRR_CMD, i, 0);
|
|
}
|
|
writel(4, &chan->msch->ddrconf);
|
|
move_to_access_state(chan);
|
|
/* DDR3 and LPDDR3 are always 8 bank, no need detect */
|
|
sdram_params->ch[channel].bk = 3;
|
|
/* Detect Col and Row number*/
|
|
ret = sdram_col_row_detect(dram, channel, sdram_params);
|
|
if (ret)
|
|
goto error;
|
|
}
|
|
/* Find NIU DDR configuration */
|
|
ret = sdram_get_niu_config(sdram_params);
|
|
if (ret)
|
|
goto error;
|
|
|
|
dram_all_config(dram, sdram_params);
|
|
debug("%s done\n", __func__);
|
|
|
|
return 0;
|
|
error:
|
|
printf("DRAM init failed!\n");
|
|
hang();
|
|
}
|
|
|
|
static int setup_sdram(struct udevice *dev)
|
|
{
|
|
struct dram_info *priv = dev_get_priv(dev);
|
|
struct rk3188_sdram_params *params = dev_get_platdata(dev);
|
|
|
|
return sdram_init(priv, params);
|
|
}
|
|
|
|
static int rk3188_dmc_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
struct rk3188_sdram_params *params = dev_get_platdata(dev);
|
|
int ret;
|
|
|
|
/* rk3188 supports only one-channel */
|
|
params->num_channels = 1;
|
|
ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
|
|
(u32 *)¶ms->pctl_timing,
|
|
sizeof(params->pctl_timing) / sizeof(u32));
|
|
if (ret) {
|
|
printf("%s: Cannot read rockchip,pctl-timing\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
ret = dev_read_u32_array(dev, "rockchip,phy-timing",
|
|
(u32 *)¶ms->phy_timing,
|
|
sizeof(params->phy_timing) / sizeof(u32));
|
|
if (ret) {
|
|
printf("%s: Cannot read rockchip,phy-timing\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
ret = dev_read_u32_array(dev, "rockchip,sdram-params",
|
|
(u32 *)¶ms->base,
|
|
sizeof(params->base) / sizeof(u32));
|
|
if (ret) {
|
|
printf("%s: Cannot read rockchip,sdram-params\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map);
|
|
if (ret)
|
|
return ret;
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_SPL_BUILD */
|
|
|
|
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
static int conv_of_platdata(struct udevice *dev)
|
|
{
|
|
struct rk3188_sdram_params *plat = dev_get_platdata(dev);
|
|
struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat;
|
|
int ret;
|
|
|
|
memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
|
|
sizeof(plat->pctl_timing));
|
|
memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
|
|
sizeof(plat->phy_timing));
|
|
memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
|
|
/* rk3188 supports dual-channel, set default channel num to 2 */
|
|
plat->num_channels = 1;
|
|
ret = regmap_init_mem_platdata(dev, of_plat->reg,
|
|
ARRAY_SIZE(of_plat->reg) / 2,
|
|
&plat->map);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static int rk3188_dmc_probe(struct udevice *dev)
|
|
{
|
|
#ifdef CONFIG_SPL_BUILD
|
|
struct rk3188_sdram_params *plat = dev_get_platdata(dev);
|
|
struct regmap *map;
|
|
struct udevice *dev_clk;
|
|
int ret;
|
|
#endif
|
|
struct dram_info *priv = dev_get_priv(dev);
|
|
|
|
priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
|
|
|
|
#ifdef CONFIG_SPL_BUILD
|
|
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
ret = conv_of_platdata(dev);
|
|
if (ret)
|
|
return ret;
|
|
#endif
|
|
map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
|
|
if (IS_ERR(map))
|
|
return PTR_ERR(map);
|
|
priv->chan[0].msch = regmap_get_range(map, 0);
|
|
|
|
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
|
|
|
priv->chan[0].pctl = regmap_get_range(plat->map, 0);
|
|
priv->chan[0].publ = regmap_get_range(plat->map, 1);
|
|
|
|
ret = rockchip_get_clk(&dev_clk);
|
|
if (ret)
|
|
return ret;
|
|
priv->ddr_clk.id = CLK_DDR;
|
|
ret = clk_request(dev_clk, &priv->ddr_clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
priv->cru = rockchip_get_cru();
|
|
if (IS_ERR(priv->cru))
|
|
return PTR_ERR(priv->cru);
|
|
ret = setup_sdram(dev);
|
|
if (ret)
|
|
return ret;
|
|
#else
|
|
priv->info.base = CONFIG_SYS_SDRAM_BASE;
|
|
priv->info.size = rockchip_sdram_size(
|
|
(phys_addr_t)&priv->pmu->sys_reg[2]);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk3188_dmc_get_info(struct udevice *dev, struct ram_info *info)
|
|
{
|
|
struct dram_info *priv = dev_get_priv(dev);
|
|
|
|
*info = priv->info;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct ram_ops rk3188_dmc_ops = {
|
|
.get_info = rk3188_dmc_get_info,
|
|
};
|
|
|
|
static const struct udevice_id rk3188_dmc_ids[] = {
|
|
{ .compatible = "rockchip,rk3188-dmc" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(rockchip_rk3188_dmc) = {
|
|
.name = "rockchip_rk3188_dmc",
|
|
.id = UCLASS_RAM,
|
|
.of_match = rk3188_dmc_ids,
|
|
.ops = &rk3188_dmc_ops,
|
|
#ifdef CONFIG_SPL_BUILD
|
|
.ofdata_to_platdata = rk3188_dmc_ofdata_to_platdata,
|
|
#endif
|
|
.probe = rk3188_dmc_probe,
|
|
.priv_auto_alloc_size = sizeof(struct dram_info),
|
|
#ifdef CONFIG_SPL_BUILD
|
|
.platdata_auto_alloc_size = sizeof(struct rk3188_sdram_params),
|
|
#endif
|
|
};
|