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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
728 lines
19 KiB
C
728 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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* Author: Andy Yan <andy.yan@rock-chips.com>
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*/
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#include <common.h>
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#include <bitfield.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <malloc.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/cru_rv1108.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <dm/lists.h>
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#include <dt-bindings/clock/rv1108-cru.h>
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#include <linux/delay.h>
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#include <linux/stringify.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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VCO_MAX_HZ = 2400U * 1000000,
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VCO_MIN_HZ = 600 * 1000000,
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OUTPUT_MAX_HZ = 2400U * 1000000,
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OUTPUT_MIN_HZ = 24 * 1000000,
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};
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
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.refdiv = _refdiv,\
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.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
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.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
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_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
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OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
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#hz "Hz cannot be hit with PLL "\
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"divisors on line " __stringify(__LINE__));
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static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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/* use integer mode */
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static inline int rv1108_pll_id(enum rk_clk_id clk_id)
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{
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int id = 0;
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switch (clk_id) {
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case CLK_ARM:
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case CLK_DDR:
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id = clk_id - 1;
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break;
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case CLK_GENERAL:
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id = 2;
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break;
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default:
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printf("invalid pll id:%d\n", clk_id);
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id = -1;
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break;
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}
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return id;
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}
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static int rkclk_set_pll(struct rv1108_cru *cru, enum rk_clk_id clk_id,
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const struct pll_div *div)
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{
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int pll_id = rv1108_pll_id(clk_id);
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struct rv1108_pll *pll = &cru->pll[pll_id];
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/* All PLLs have same VCO and output frequency range restrictions. */
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uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
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uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
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debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
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pll, div->fbdiv, div->refdiv, div->postdiv1,
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div->postdiv2, vco_hz, output_hz);
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assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
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output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
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/*
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* When power on or changing PLL setting,
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* we must force PLL into slow mode to ensure output stable clock.
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*/
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rk_clrsetreg(&pll->con3, WORK_MODE_MASK,
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WORK_MODE_SLOW << WORK_MODE_SHIFT);
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/* use integer mode */
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rk_setreg(&pll->con3, 1 << DSMPD_SHIFT);
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/* Power down */
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rk_setreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT);
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rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT);
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rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK,
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(div->postdiv1 << POSTDIV1_SHIFT |
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div->postdiv2 << POSTDIV2_SHIFT |
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div->refdiv << REFDIV_SHIFT));
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rk_clrsetreg(&pll->con2, FRACDIV_MASK,
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(div->refdiv << REFDIV_SHIFT));
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/* Power Up */
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rk_clrreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT);
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/* waiting for pll lock */
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while (readl(&pll->con2) & (1 << LOCK_STA_SHIFT))
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udelay(1);
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/*
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* set PLL into normal mode.
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*/
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rk_clrsetreg(&pll->con3, WORK_MODE_MASK,
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WORK_MODE_NORMAL << WORK_MODE_SHIFT);
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return 0;
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}
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static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru,
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enum rk_clk_id clk_id)
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{
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uint32_t refdiv, fbdiv, postdiv1, postdiv2;
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uint32_t con0, con1, con3;
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int pll_id = rv1108_pll_id(clk_id);
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struct rv1108_pll *pll = &cru->pll[pll_id];
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uint32_t freq;
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con3 = readl(&pll->con3);
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if (con3 & WORK_MODE_MASK) {
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con0 = readl(&pll->con0);
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con1 = readl(&pll->con1);
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fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK;
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postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT;
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postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT;
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refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK;
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freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
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} else {
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freq = OSC_HZ;
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}
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return freq;
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}
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static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate)
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{
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uint32_t con = readl(&cru->clksel_con[24]);
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ulong pll_rate;
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uint8_t div;
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if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL)
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pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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else
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pll_rate = rkclk_pll_get_rate(cru, CLK_ARM);
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/*default set 50MHZ for gmac*/
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if (!rate)
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rate = 50000000;
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div = DIV_ROUND_UP(pll_rate, rate) - 1;
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if (div <= 0x1f)
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rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK,
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div << MAC_CLK_DIV_SHIFT);
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else
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debug("Unsupported div for gmac:%d\n", div);
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return DIV_TO_RATE(pll_rate, div);
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}
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static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate)
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{
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u32 con = readl(&cru->clksel_con[27]);
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u32 pll_rate;
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u32 div;
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if ((con >> SFC_PLL_SEL_SHIFT) && SFC_PLL_SEL_GPLL)
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pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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else
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pll_rate = rkclk_pll_get_rate(cru, CLK_DDR);
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div = DIV_ROUND_UP(pll_rate, rate) - 1;
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if (div <= 0x3f)
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rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK,
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div << SFC_CLK_DIV_SHIFT);
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else
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debug("Unsupported sfc clk rate:%d\n", rate);
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return DIV_TO_RATE(pll_rate, div);
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}
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static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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val = readl(&cru->clksel_con[22]);
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div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
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CLK_SARADC_DIV_CON_WIDTH);
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return DIV_TO_RATE(OSC_HZ, div);
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}
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static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
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assert(src_clk_div < 128);
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rk_clrsetreg(&cru->clksel_con[22],
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CLK_SARADC_DIV_CON_MASK,
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src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
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return rv1108_saradc_get_clk(cru);
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}
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static ulong rv1108_aclk_vio1_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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val = readl(&cru->clksel_con[28]);
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div = bitfield_extract(val, ACLK_VIO1_CLK_DIV_SHIFT,
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CLK_VIO_DIV_CON_WIDTH);
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return DIV_TO_RATE(GPLL_HZ, div);
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}
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static ulong rv1108_aclk_vio1_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
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assert(src_clk_div < 32);
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rk_clrsetreg(&cru->clksel_con[28],
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ACLK_VIO1_CLK_DIV_MASK | ACLK_VIO1_PLL_SEL_MASK,
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(src_clk_div << ACLK_VIO1_CLK_DIV_SHIFT) |
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(VIO_PLL_SEL_GPLL << ACLK_VIO1_PLL_SEL_SHIFT));
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return rv1108_aclk_vio1_get_clk(cru);
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}
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static ulong rv1108_aclk_vio0_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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val = readl(&cru->clksel_con[28]);
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div = bitfield_extract(val, ACLK_VIO0_CLK_DIV_SHIFT,
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CLK_VIO_DIV_CON_WIDTH);
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return DIV_TO_RATE(GPLL_HZ, div);
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}
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static ulong rv1108_aclk_vio0_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
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assert(src_clk_div < 32);
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rk_clrsetreg(&cru->clksel_con[28],
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ACLK_VIO0_CLK_DIV_MASK | ACLK_VIO0_PLL_SEL_MASK,
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(src_clk_div << ACLK_VIO0_CLK_DIV_SHIFT) |
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(VIO_PLL_SEL_GPLL << ACLK_VIO0_PLL_SEL_SHIFT));
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/*HCLK_VIO default div = 4*/
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rk_clrsetreg(&cru->clksel_con[29],
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HCLK_VIO_CLK_DIV_MASK,
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3 << HCLK_VIO_CLK_DIV_SHIFT);
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/*PCLK_VIO default div = 4*/
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rk_clrsetreg(&cru->clksel_con[29],
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PCLK_VIO_CLK_DIV_MASK,
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3 << PCLK_VIO_CLK_DIV_SHIFT);
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return rv1108_aclk_vio0_get_clk(cru);
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}
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static ulong rv1108_dclk_vop_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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val = readl(&cru->clksel_con[32]);
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div = bitfield_extract(val, DCLK_VOP_CLK_DIV_SHIFT,
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DCLK_VOP_DIV_CON_WIDTH);
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return DIV_TO_RATE(GPLL_HZ, div);
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}
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static ulong rv1108_dclk_vop_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
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assert(src_clk_div < 64);
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rk_clrsetreg(&cru->clksel_con[32],
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DCLK_VOP_CLK_DIV_MASK | DCLK_VOP_PLL_SEL_MASK |
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DCLK_VOP_SEL_SHIFT,
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(src_clk_div << DCLK_VOP_CLK_DIV_SHIFT) |
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(DCLK_VOP_PLL_SEL_GPLL << DCLK_VOP_PLL_SEL_SHIFT) |
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(DCLK_VOP_SEL_PLL << DCLK_VOP_SEL_SHIFT));
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return rv1108_dclk_vop_get_clk(cru);
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}
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static ulong rv1108_aclk_bus_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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val = readl(&cru->clksel_con[2]);
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div = bitfield_extract(val, ACLK_BUS_DIV_CON_SHIFT,
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ACLK_BUS_DIV_CON_WIDTH);
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return DIV_TO_RATE(parent_rate, div);
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}
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static ulong rv1108_aclk_bus_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
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assert(src_clk_div < 32);
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rk_clrsetreg(&cru->clksel_con[2],
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ACLK_BUS_DIV_CON_MASK | ACLK_BUS_PLL_SEL_MASK,
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(src_clk_div << ACLK_BUS_DIV_CON_SHIFT) |
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(ACLK_BUS_PLL_SEL_GPLL << ACLK_BUS_PLL_SEL_SHIFT));
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return rv1108_aclk_bus_get_clk(cru);
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}
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static ulong rv1108_aclk_peri_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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val = readl(&cru->clksel_con[23]);
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div = bitfield_extract(val, ACLK_PERI_DIV_CON_SHIFT,
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PERI_DIV_CON_WIDTH);
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return DIV_TO_RATE(parent_rate, div);
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}
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static ulong rv1108_hclk_peri_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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val = readl(&cru->clksel_con[23]);
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div = bitfield_extract(val, HCLK_PERI_DIV_CON_SHIFT,
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PERI_DIV_CON_WIDTH);
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return DIV_TO_RATE(parent_rate, div);
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}
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static ulong rv1108_pclk_peri_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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val = readl(&cru->clksel_con[23]);
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div = bitfield_extract(val, PCLK_PERI_DIV_CON_SHIFT,
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PERI_DIV_CON_WIDTH);
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return DIV_TO_RATE(parent_rate, div);
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}
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static ulong rv1108_aclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
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assert(src_clk_div < 32);
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rk_clrsetreg(&cru->clksel_con[23],
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ACLK_PERI_DIV_CON_MASK | ACLK_PERI_PLL_SEL_MASK,
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(src_clk_div << ACLK_PERI_DIV_CON_SHIFT) |
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(ACLK_PERI_PLL_SEL_GPLL << ACLK_PERI_PLL_SEL_SHIFT));
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return rv1108_aclk_peri_get_clk(cru);
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}
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static ulong rv1108_hclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
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assert(src_clk_div < 32);
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rk_clrsetreg(&cru->clksel_con[23],
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HCLK_PERI_DIV_CON_MASK,
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(src_clk_div << HCLK_PERI_DIV_CON_SHIFT));
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return rv1108_hclk_peri_get_clk(cru);
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}
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static ulong rv1108_pclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
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assert(src_clk_div < 32);
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rk_clrsetreg(&cru->clksel_con[23],
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PCLK_PERI_DIV_CON_MASK,
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(src_clk_div << PCLK_PERI_DIV_CON_SHIFT));
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return rv1108_pclk_peri_get_clk(cru);
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}
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static ulong rv1108_i2c_get_clk(struct rv1108_cru *cru, ulong clk_id)
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{
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u32 div, con;
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switch (clk_id) {
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case SCLK_I2C0_PMU:
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con = readl(&cru->clksel_con[19]);
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div = bitfield_extract(con, CLK_I2C0_DIV_CON_SHIFT,
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I2C_DIV_CON_WIDTH);
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break;
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case SCLK_I2C1:
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con = readl(&cru->clksel_con[19]);
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div = bitfield_extract(con, CLK_I2C1_DIV_CON_SHIFT,
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I2C_DIV_CON_WIDTH);
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break;
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case SCLK_I2C2:
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con = readl(&cru->clksel_con[20]);
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div = bitfield_extract(con, CLK_I2C2_DIV_CON_SHIFT,
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I2C_DIV_CON_WIDTH);
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break;
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case SCLK_I2C3:
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con = readl(&cru->clksel_con[20]);
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div = bitfield_extract(con, CLK_I2C3_DIV_CON_SHIFT,
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I2C_DIV_CON_WIDTH);
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break;
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default:
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printf("do not support this i2c bus\n");
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return -EINVAL;
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}
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return DIV_TO_RATE(GPLL_HZ, div);
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}
|
|
|
|
static ulong rv1108_i2c_set_clk(struct rv1108_cru *cru, ulong clk_id, uint hz)
|
|
{
|
|
int src_clk_div;
|
|
|
|
/* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
|
|
src_clk_div = GPLL_HZ / hz;
|
|
assert(src_clk_div - 1 <= 127);
|
|
|
|
switch (clk_id) {
|
|
case SCLK_I2C0_PMU:
|
|
rk_clrsetreg(&cru->clksel_con[19],
|
|
CLK_I2C0_DIV_CON_MASK | CLK_I2C1_PLL_SEL_MASK,
|
|
(src_clk_div << CLK_I2C0_DIV_CON_SHIFT) |
|
|
(CLK_I2C1_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT));
|
|
break;
|
|
case SCLK_I2C1:
|
|
rk_clrsetreg(&cru->clksel_con[19],
|
|
CLK_I2C1_DIV_CON_MASK | CLK_I2C1_PLL_SEL_MASK,
|
|
(src_clk_div << CLK_I2C1_DIV_CON_SHIFT) |
|
|
(CLK_I2C1_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT));
|
|
break;
|
|
case SCLK_I2C2:
|
|
rk_clrsetreg(&cru->clksel_con[20],
|
|
CLK_I2C2_DIV_CON_MASK | CLK_I2C3_PLL_SEL_MASK,
|
|
(src_clk_div << CLK_I2C2_DIV_CON_SHIFT) |
|
|
(CLK_I2C3_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT));
|
|
break;
|
|
case SCLK_I2C3:
|
|
rk_clrsetreg(&cru->clksel_con[20],
|
|
CLK_I2C3_DIV_CON_MASK | CLK_I2C3_PLL_SEL_MASK,
|
|
(src_clk_div << CLK_I2C3_DIV_CON_SHIFT) |
|
|
(CLK_I2C3_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT));
|
|
break;
|
|
default:
|
|
printf("do not support this i2c bus\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return rv1108_i2c_get_clk(cru, clk_id);
|
|
}
|
|
|
|
static ulong rv1108_mmc_get_clk(struct rv1108_cru *cru)
|
|
{
|
|
u32 div, con;
|
|
ulong mmc_clk;
|
|
|
|
con = readl(&cru->clksel_con[26]);
|
|
div = bitfield_extract(con, EMMC_CLK_DIV_SHIFT, 8);
|
|
|
|
con = readl(&cru->clksel_con[25]);
|
|
|
|
if ((con & EMMC_PLL_SEL_MASK) >> EMMC_PLL_SEL_SHIFT == EMMC_PLL_SEL_OSC)
|
|
mmc_clk = DIV_TO_RATE(OSC_HZ, div) / 2;
|
|
else
|
|
mmc_clk = DIV_TO_RATE(GPLL_HZ, div) / 2;
|
|
|
|
debug("%s div %d get_clk %ld\n", __func__, div, mmc_clk);
|
|
return mmc_clk;
|
|
}
|
|
|
|
static ulong rv1108_mmc_set_clk(struct rv1108_cru *cru, ulong rate)
|
|
{
|
|
int div;
|
|
u32 pll_rate;
|
|
|
|
div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, CLK_GENERAL), rate);
|
|
|
|
if (div < 127) {
|
|
debug("%s source gpll\n", __func__);
|
|
rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK,
|
|
(EMMC_PLL_SEL_GPLL << EMMC_PLL_SEL_SHIFT));
|
|
pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
|
|
} else {
|
|
debug("%s source 24m\n", __func__);
|
|
rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK,
|
|
(EMMC_PLL_SEL_OSC << EMMC_PLL_SEL_SHIFT));
|
|
pll_rate = OSC_HZ;
|
|
}
|
|
|
|
div = DIV_ROUND_UP(pll_rate / 2, rate);
|
|
rk_clrsetreg(&cru->clksel_con[26], EMMC_CLK_DIV_MASK,
|
|
((div - 1) << EMMC_CLK_DIV_SHIFT));
|
|
|
|
debug("%s set_rate %ld div %d\n", __func__, rate, div);
|
|
|
|
return DIV_TO_RATE(pll_rate, div);
|
|
}
|
|
|
|
static ulong rv1108_clk_get_rate(struct clk *clk)
|
|
{
|
|
struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
|
|
|
|
switch (clk->id) {
|
|
case 0 ... 63:
|
|
return rkclk_pll_get_rate(priv->cru, clk->id);
|
|
case SCLK_SARADC:
|
|
return rv1108_saradc_get_clk(priv->cru);
|
|
case ACLK_VIO0:
|
|
return rv1108_aclk_vio0_get_clk(priv->cru);
|
|
case ACLK_VIO1:
|
|
return rv1108_aclk_vio1_get_clk(priv->cru);
|
|
case DCLK_VOP:
|
|
return rv1108_dclk_vop_get_clk(priv->cru);
|
|
case ACLK_PRE:
|
|
return rv1108_aclk_bus_get_clk(priv->cru);
|
|
case ACLK_PERI:
|
|
return rv1108_aclk_peri_get_clk(priv->cru);
|
|
case HCLK_PERI:
|
|
return rv1108_hclk_peri_get_clk(priv->cru);
|
|
case PCLK_PERI:
|
|
return rv1108_pclk_peri_get_clk(priv->cru);
|
|
case SCLK_I2C0_PMU:
|
|
case SCLK_I2C1:
|
|
case SCLK_I2C2:
|
|
case SCLK_I2C3:
|
|
return rv1108_i2c_get_clk(priv->cru, clk->id);
|
|
case HCLK_EMMC:
|
|
case SCLK_EMMC:
|
|
case SCLK_EMMC_SAMPLE:
|
|
return rv1108_mmc_get_clk(priv->cru);
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
}
|
|
|
|
static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
|
|
ulong new_rate;
|
|
|
|
switch (clk->id) {
|
|
case SCLK_MAC:
|
|
new_rate = rv1108_mac_set_clk(priv->cru, rate);
|
|
break;
|
|
case SCLK_SFC:
|
|
new_rate = rv1108_sfc_set_clk(priv->cru, rate);
|
|
break;
|
|
case SCLK_SARADC:
|
|
new_rate = rv1108_saradc_set_clk(priv->cru, rate);
|
|
break;
|
|
case ACLK_VIO0:
|
|
new_rate = rv1108_aclk_vio0_set_clk(priv->cru, rate);
|
|
break;
|
|
case ACLK_VIO1:
|
|
new_rate = rv1108_aclk_vio1_set_clk(priv->cru, rate);
|
|
break;
|
|
case DCLK_VOP:
|
|
new_rate = rv1108_dclk_vop_set_clk(priv->cru, rate);
|
|
break;
|
|
case ACLK_PRE:
|
|
new_rate = rv1108_aclk_bus_set_clk(priv->cru, rate);
|
|
break;
|
|
case ACLK_PERI:
|
|
new_rate = rv1108_aclk_peri_set_clk(priv->cru, rate);
|
|
break;
|
|
case HCLK_PERI:
|
|
new_rate = rv1108_hclk_peri_set_clk(priv->cru, rate);
|
|
break;
|
|
case PCLK_PERI:
|
|
new_rate = rv1108_pclk_peri_set_clk(priv->cru, rate);
|
|
break;
|
|
case SCLK_I2C0_PMU:
|
|
case SCLK_I2C1:
|
|
case SCLK_I2C2:
|
|
case SCLK_I2C3:
|
|
new_rate = rv1108_i2c_set_clk(priv->cru, clk->id, rate);
|
|
break;
|
|
case HCLK_EMMC:
|
|
case SCLK_EMMC:
|
|
new_rate = rv1108_mmc_set_clk(priv->cru, rate);
|
|
break;
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
return new_rate;
|
|
}
|
|
|
|
static const struct clk_ops rv1108_clk_ops = {
|
|
.get_rate = rv1108_clk_get_rate,
|
|
.set_rate = rv1108_clk_set_rate,
|
|
};
|
|
|
|
static void rkclk_init(struct rv1108_cru *cru)
|
|
{
|
|
unsigned int apll, dpll, gpll;
|
|
unsigned int aclk_bus, aclk_peri, hclk_peri, pclk_peri;
|
|
|
|
aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ / 2);
|
|
aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ / 2);
|
|
hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ / 2);
|
|
pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ / 2);
|
|
rv1108_aclk_vio0_set_clk(cru, 297000000);
|
|
rv1108_aclk_vio1_set_clk(cru, 297000000);
|
|
|
|
/* configure apll */
|
|
rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
|
|
rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
|
|
aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ);
|
|
aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ);
|
|
hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ);
|
|
pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ);
|
|
|
|
apll = rkclk_pll_get_rate(cru, CLK_ARM);
|
|
dpll = rkclk_pll_get_rate(cru, CLK_DDR);
|
|
gpll = rkclk_pll_get_rate(cru, CLK_GENERAL);
|
|
|
|
rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK,
|
|
0 << MAC_CLK_DIV_SHIFT);
|
|
|
|
printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
|
|
printf("ACLK_BUS: %d ACLK_PERI:%d HCLK_PERI:%d PCLK_PERI:%d\n",
|
|
aclk_bus, aclk_peri, hclk_peri, pclk_peri);
|
|
}
|
|
|
|
static int rv1108_clk_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct rv1108_clk_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->cru = dev_read_addr_ptr(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rv1108_clk_probe(struct udevice *dev)
|
|
{
|
|
struct rv1108_clk_priv *priv = dev_get_priv(dev);
|
|
|
|
rkclk_init(priv->cru);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rv1108_clk_bind(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
struct udevice *sys_child;
|
|
struct sysreset_reg *priv;
|
|
|
|
/* The reset driver does not have a device node, so bind it here */
|
|
ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
|
|
&sys_child);
|
|
if (ret) {
|
|
debug("Warning: No sysreset driver: ret=%d\n", ret);
|
|
} else {
|
|
priv = malloc(sizeof(struct sysreset_reg));
|
|
priv->glb_srst_fst_value = offsetof(struct rv1108_cru,
|
|
glb_srst_fst_val);
|
|
priv->glb_srst_snd_value = offsetof(struct rv1108_cru,
|
|
glb_srst_snd_val);
|
|
sys_child->priv = priv;
|
|
}
|
|
|
|
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
|
|
ret = offsetof(struct rv1108_cru, softrst_con[0]);
|
|
ret = rockchip_reset_bind(dev, ret, 13);
|
|
if (ret)
|
|
debug("Warning: software reset driver bind faile\n");
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id rv1108_clk_ids[] = {
|
|
{ .compatible = "rockchip,rv1108-cru" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(clk_rv1108) = {
|
|
.name = "clk_rv1108",
|
|
.id = UCLASS_CLK,
|
|
.of_match = rv1108_clk_ids,
|
|
.priv_auto_alloc_size = sizeof(struct rv1108_clk_priv),
|
|
.ops = &rv1108_clk_ops,
|
|
.bind = rv1108_clk_bind,
|
|
.ofdata_to_platdata = rv1108_clk_ofdata_to_platdata,
|
|
.probe = rv1108_clk_probe,
|
|
};
|