mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-27 04:18:51 +09:00
![Teresa Remmet](/assets/img/avatar_default.png)
Add initial support PHYTEC phyCORE-i.MX8MP SOM. Supported features: - 2GB LPDDR4 RAM - eMMC - external SD - debug UART2 - watchdog Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Heiko Schocher <hs@denx.de>
294 lines
7.0 KiB
Plaintext
294 lines
7.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (C) 2020 PHYTEC Messtechnik GmbH
|
|
* Author: Teresa Remmet <t.remmet@phytec.de>
|
|
*/
|
|
|
|
#include <dt-bindings/net/ti-dp83867.h>
|
|
#include "imx8mp.dtsi"
|
|
|
|
/ {
|
|
model = "PHYTEC phyCORE-i.MX8MP";
|
|
compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
|
|
|
|
aliases {
|
|
rtc0 = &rv3028;
|
|
rtc1 = &snvs_rtc;
|
|
};
|
|
|
|
memory@40000000 {
|
|
device_type = "memory";
|
|
reg = <0x0 0x40000000 0 0x80000000>;
|
|
};
|
|
};
|
|
|
|
&A53_0 {
|
|
cpu-supply = <&buck2>;
|
|
};
|
|
|
|
&A53_1 {
|
|
cpu-supply = <&buck2>;
|
|
};
|
|
|
|
&A53_2 {
|
|
cpu-supply = <&buck2>;
|
|
};
|
|
|
|
&A53_3 {
|
|
cpu-supply = <&buck2>;
|
|
};
|
|
|
|
/* ethernet 1 */
|
|
&fec {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_fec>;
|
|
phy-mode = "rgmii-id";
|
|
phy-handle = <ðphy1>;
|
|
fsl,magic-packet;
|
|
status = "okay";
|
|
|
|
mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ethphy1: ethernet-phy@0 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <0>;
|
|
interrupt-parent = <&gpio1>;
|
|
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
|
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
|
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
|
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
|
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
|
|
enet-phy-lane-no-swap;
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c1 {
|
|
clock-frequency = <400000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
|
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
status = "okay";
|
|
|
|
pmic: pmic@25 {
|
|
reg = <0x25>;
|
|
compatible = "nxp,pca9450c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pmic>;
|
|
interrupt-parent = <&gpio4>;
|
|
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
|
|
|
|
regulators {
|
|
buck1: BUCK1 {
|
|
regulator-compatible = "BUCK1";
|
|
regulator-min-microvolt = <600000>;
|
|
regulator-max-microvolt = <2187500>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
regulator-ramp-delay = <3125>;
|
|
};
|
|
|
|
buck2: BUCK2 {
|
|
regulator-compatible = "BUCK2";
|
|
regulator-min-microvolt = <600000>;
|
|
regulator-max-microvolt = <2187500>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
regulator-ramp-delay = <3125>;
|
|
};
|
|
|
|
buck4: BUCK4 {
|
|
regulator-compatible = "BUCK4";
|
|
regulator-min-microvolt = <600000>;
|
|
regulator-max-microvolt = <3400000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
buck5: BUCK5 {
|
|
regulator-compatible = "BUCK5";
|
|
regulator-min-microvolt = <600000>;
|
|
regulator-max-microvolt = <3400000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
buck6: BUCK6 {
|
|
regulator-compatible = "BUCK6";
|
|
regulator-min-microvolt = <600000>;
|
|
regulator-max-microvolt = <3400000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo1: LDO1 {
|
|
regulator-compatible = "LDO1";
|
|
regulator-min-microvolt = <1600000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo2: LDO2 {
|
|
regulator-compatible = "LDO2";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1150000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo3: LDO3 {
|
|
regulator-compatible = "LDO3";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo4: LDO4 {
|
|
regulator-compatible = "LDO4";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo5: LDO5 {
|
|
regulator-compatible = "LDO5";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
eeprom@51 {
|
|
compatible = "atmel,24c32";
|
|
reg = <0x51>;
|
|
pagesize = <32>;
|
|
};
|
|
|
|
rv3028: rtc@52 {
|
|
compatible = "microcrystal,rv3028";
|
|
reg = <0x52>;
|
|
trickle-resistor-ohms = <3000>;
|
|
};
|
|
};
|
|
|
|
/* eMMC */
|
|
&usdhc3 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc3>;
|
|
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
|
bus-width = <8>;
|
|
non-removable;
|
|
status = "okay";
|
|
};
|
|
|
|
&wdog1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
|
fsl,ext-reset-output;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl_fec: fecgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
|
|
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
|
|
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
|
|
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
|
|
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
|
|
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
|
|
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
|
|
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
|
|
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
|
|
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
|
|
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
|
|
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
|
|
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
|
|
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
|
|
MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
|
|
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1_gpio: i2c1gpiogrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3
|
|
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3
|
|
>;
|
|
};
|
|
|
|
pinctrl_pmic: pmicirqgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
|
|
>;
|
|
};
|
|
};
|