mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-31 07:13:44 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
67 lines
1.9 KiB
C
67 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* From Coreboot file of the same name
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*
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* Copyright (C) 2011 The ChromiumOS Authors.
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*/
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#ifndef _ASM_ARCH_MODEL_206AX_H
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#define _ASM_ARCH_MODEL_206AX_H
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/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
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#define SANDYBRIDGE_BCLK 100
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#define CPUID_VMX (1 << 5)
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#define CPUID_SMX (1 << 6)
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#define MSR_FEATURE_CONFIG 0x13c
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#define IA32_PLATFORM_DCA_CAP 0x1f8
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#define IA32_MISC_ENABLE 0x1a0
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#define MSR_TEMPERATURE_TARGET 0x1a2
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#define IA32_THERM_INTERRUPT 0x19b
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#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
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#define ENERGY_POLICY_PERFORMANCE 0
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#define ENERGY_POLICY_NORMAL 6
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#define ENERGY_POLICY_POWERSAVE 15
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#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
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#define MSR_LT_LOCK_MEMORY 0x2e7
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#define IA32_MC0_STATUS 0x401
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#define MSR_MISC_PWR_MGMT 0x1aa
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#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
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#define MSR_PKGC3_IRTL 0x60a
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#define MSR_PKGC6_IRTL 0x60b
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#define MSR_PKGC7_IRTL 0x60c
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#define IRTL_VALID (1 << 15)
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#define IRTL_1_NS (0 << 10)
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#define IRTL_32_NS (1 << 10)
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#define IRTL_1024_NS (2 << 10)
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#define IRTL_32768_NS (3 << 10)
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#define IRTL_1048576_NS (4 << 10)
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#define IRTL_33554432_NS (5 << 10)
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#define IRTL_RESPONSE_MASK (0x3ff)
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#define MSR_PP0_CURRENT_CONFIG 0x601
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#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */
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#define MSR_PP1_CURRENT_CONFIG 0x602
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#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */
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#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */
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#define MSR_PKG_POWER_SKU 0x614
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#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2
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#define MSR_CONFIG_TDP_LEVEL1 0x649
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#define MSR_CONFIG_TDP_LEVEL2 0x64a
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#define MSR_CONFIG_TDP_CONTROL 0x64b
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/* P-state configuration */
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#define PSS_MAX_ENTRIES 8
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#define PSS_RATIO_STEP 2
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#define PSS_LATENCY_TRANSITION 10
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#define PSS_LATENCY_BUSMASTER 10
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/* Configure power limits for turbo mode */
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void set_power_limits(u8 power_limit_1_time);
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int cpu_config_tdp_levels(void);
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#endif
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