mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
2d86ab50ce
Without the prefix, "same-as-spl" in `u-boot,spl-boot-order` will not work as expected. When board_boot_order() `spl-boot-order.c` meets "same-as-spl", it gets the conf by looking the boot_devices table by boot source, and parse the node by the conf with: node = fdt_path_offset(blob, conf); which will failed without the "/" indicating the path. Currently only entries of boot_devices in rk3399 have the "/" prefix. Therefore add the missing ones in other boards. Signed-off-by: Levin Du <djw@t-chip.com.cn> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
74 lines
1.9 KiB
C
74 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/grf_rk322x.h>
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#include <asm/arch-rockchip/hardware.h>
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/dwmmc@30020000",
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[BROM_BOOTSOURCE_SD] = "/dwmmc@30000000",
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};
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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#define GRF_BASE 0x11000000
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static struct rk322x_grf * const grf = (void *)GRF_BASE;
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enum {
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GPIO1B2_SHIFT = 4,
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GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
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GPIO1B2_GPIO = 0,
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GPIO1B2_UART1_SIN,
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GPIO1B2_UART21_SIN,
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GPIO1B1_SHIFT = 2,
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GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
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GPIO1B1_GPIO = 0,
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GPIO1B1_UART1_SOUT,
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GPIO1B1_UART21_SOUT,
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};
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enum {
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CON_IOMUX_UART2SEL_SHIFT = 8,
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CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
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CON_IOMUX_UART2SEL_2 = 0,
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CON_IOMUX_UART2SEL_21,
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};
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/* Enable early UART2 channel 1 on the RK322x */
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rk_clrsetreg(&grf->gpio1b_iomux,
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GPIO1B1_MASK | GPIO1B2_MASK,
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GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
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GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
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/* Set channel C as UART2 input */
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rk_clrsetreg(&grf->con_iomux,
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CON_IOMUX_UART2SEL_MASK,
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CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
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}
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#endif
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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#define SGRF_BASE 0x10150000
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static struct rk322x_sgrf * const sgrf = (void *)SGRF_BASE;
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/* Disable the ddr secure region setting to make it non-secure */
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rk_clrreg(&sgrf->soc_con[0], 0x4000);
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#else
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#define GRF_BASE 0x11000000
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static struct rk322x_grf * const grf = (void *)GRF_BASE;
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/*
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* The integrated macphy is enabled by default, disable it
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* for saving power consuming.
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*/
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rk_clrsetreg(&grf->macphy_con[0],
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MACPHY_CFG_ENABLE_MASK,
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0 << MACPHY_CFG_ENABLE_SHIFT);
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#endif
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return 0;
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}
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