mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
95 lines
2.2 KiB
C
95 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 Google, Inc
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*
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* Memory Type Range Regsters - these are used to tell the CPU whether
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* memory is cacheable and if so the cache write mode to use.
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*
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* These can speed up booting. See the mtrr command.
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*
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* Reference: Intel Architecture Software Developer's Manual, Volume 3:
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* System Programming
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Prepare to adjust MTRRs */
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void mtrr_open(struct mtrr_state *state)
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{
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if (!gd->arch.has_mtrr)
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return;
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state->enable_cache = dcache_status();
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if (state->enable_cache)
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disable_caches();
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state->deftype = native_read_msr(MTRR_DEF_TYPE_MSR);
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wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN);
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}
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/* Clean up after adjusting MTRRs, and enable them */
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void mtrr_close(struct mtrr_state *state)
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{
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if (!gd->arch.has_mtrr)
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return;
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wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN);
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if (state->enable_cache)
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enable_caches();
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}
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int mtrr_commit(bool do_caches)
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{
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struct mtrr_request *req = gd->arch.mtrr_req;
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struct mtrr_state state;
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uint64_t mask;
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int i;
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if (!gd->arch.has_mtrr)
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return -ENOSYS;
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mtrr_open(&state);
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for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) {
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mask = ~(req->size - 1);
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mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
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wrmsrl(MTRR_PHYS_BASE_MSR(i), req->start | req->type);
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wrmsrl(MTRR_PHYS_MASK_MSR(i), mask | MTRR_PHYS_MASK_VALID);
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}
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/* Clear the ones that are unused */
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for (; i < MTRR_COUNT; i++)
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wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
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mtrr_close(&state);
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return 0;
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}
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int mtrr_add_request(int type, uint64_t start, uint64_t size)
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{
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struct mtrr_request *req;
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uint64_t mask;
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if (!gd->arch.has_mtrr)
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return -ENOSYS;
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if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
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return -ENOSPC;
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req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
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req->type = type;
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req->start = start;
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req->size = size;
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debug("%d: type=%d, %08llx %08llx\n", gd->arch.mtrr_req_count - 1,
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req->type, req->start, req->size);
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mask = ~(req->size - 1);
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mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
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mask |= MTRR_PHYS_MASK_VALID;
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debug(" %016llx %016llx\n", req->start | req->type, mask);
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return 0;
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}
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