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![Haavard Skinnemoen](/assets/img/avatar_default.png)
Driver for the Atmel MCI controller (MMC interface) for AT32AP CPUs. The AT91 ARM-based CPUs use basically the same hardware, so it should be possible to share this driver, but no effort has been made so far. Hardware documentation can be found in the AT32AP7000 data sheet, which can be downloaded from http://www.atmel.com/dyn/products/datasheets.asp?family_id=682 Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
97 lines
2.3 KiB
C
97 lines
2.3 KiB
C
/*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_AVR32_MMC_H
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#define __ASM_AVR32_MMC_H
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struct mmc_cid {
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unsigned long psn;
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unsigned short oid;
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unsigned char mid;
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unsigned char prv;
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unsigned char mdt;
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char pnm[7];
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};
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struct mmc_csd
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{
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u8 csd_structure:2,
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spec_vers:4,
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rsvd1:2;
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u8 taac;
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u8 nsac;
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u8 tran_speed;
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u16 ccc:12,
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read_bl_len:4;
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u64 read_bl_partial:1,
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write_blk_misalign:1,
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read_blk_misalign:1,
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dsr_imp:1,
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rsvd2:2,
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c_size:12,
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vdd_r_curr_min:3,
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vdd_r_curr_max:3,
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vdd_w_curr_min:3,
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vdd_w_curr_max:3,
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c_size_mult:3,
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sector_size:5,
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erase_grp_size:5,
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wp_grp_size:5,
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wp_grp_enable:1,
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default_ecc:2,
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r2w_factor:3,
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write_bl_len:4,
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write_bl_partial:1,
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rsvd3:5;
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u8 file_format_grp:1,
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copy:1,
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perm_write_protect:1,
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tmp_write_protect:1,
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file_format:2,
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ecc:2;
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u8 crc:7;
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u8 one:1;
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};
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/* MMC Command numbers */
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#define MMC_CMD_GO_IDLE_STATE 0
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#define MMC_CMD_SEND_OP_COND 1
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#define MMC_CMD_ALL_SEND_CID 2
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#define MMC_CMD_SET_RELATIVE_ADDR 3
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#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3
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#define MMC_CMD_SET_DSR 4
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#define MMC_CMD_SELECT_CARD 7
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#define MMC_CMD_SEND_CSD 9
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#define MMC_CMD_SEND_CID 10
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#define MMC_CMD_SEND_STATUS 13
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#define MMC_CMD_SET_BLOCKLEN 16
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#define MMC_CMD_READ_SINGLE_BLOCK 17
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#define MMC_CMD_READ_MULTIPLE_BLOCK 18
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#define MMC_CMD_WRITE_BLOCK 24
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#define MMC_CMD_APP_CMD 55
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#define MMC_ACMD_SD_SEND_OP_COND 41
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#define R1_ILLEGAL_COMMAND (1 << 22)
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#define R1_APP_CMD (1 << 5)
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#endif /* __ASM_AVR32_MMC_H */
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