mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
136 lines
3.8 KiB
C
136 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Authors: Priyanka Jain <Priyanka.Jain@freescale.com>
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* Wang Dongsheng <dongsheng.wang@freescale.com>
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*
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* This file is copied and modified from the original t1040qds/diu.c.
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* Encoder can be used in T104x and LSx Platform.
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*/
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#include <common.h>
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#include <stdio_dev.h>
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#include <i2c.h>
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#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F
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#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33
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#define I2C_DVI_PLL_DIVIDER_REG 0x34
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#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35
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#define I2C_DVI_PLL_FILTER_REG 0x36
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#define I2C_DVI_TEST_PATTERN_REG 0x48
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#define I2C_DVI_POWER_MGMT_REG 0x49
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#define I2C_DVI_LOCK_STATE_REG 0x4D
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#define I2C_DVI_SYNC_POLARITY_REG 0x56
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/*
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* Set VSYNC/HSYNC to active high. This is polarity of sync signals
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* from DIU->DVI. The DIU default is active igh, so DVI is set to
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* active high.
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*/
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#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98
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#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
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#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26
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#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0
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#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08
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#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16
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#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60
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/* Clear test pattern */
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#define I2C_DVI_TEST_PATTERN_VAL 0x18
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/* Exit Power-down mode */
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#define I2C_DVI_POWER_MGMT_VAL 0xC0
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/* Monitor polarity is handled via DVI Sync Polarity Register */
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#define I2C_DVI_SYNC_POLARITY_VAL 0x00
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/* Programming of HDMI Chrontel CH7301 connector */
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int diu_set_dvi_encoder(unsigned int pixclock)
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{
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int ret;
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u8 temp;
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temp = I2C_DVI_TEST_PATTERN_VAL;
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
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&temp, 1);
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if (ret) {
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puts("I2C: failed to select proper dvi test pattern\n");
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return ret;
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}
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temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
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1, &temp, 1);
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if (ret) {
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puts("I2C: failed to select dvi input data format\n");
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return ret;
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}
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/* Set Sync polarity register */
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temp = I2C_DVI_SYNC_POLARITY_VAL;
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
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&temp, 1);
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if (ret) {
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puts("I2C: failed to select dvi syc polarity\n");
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return ret;
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}
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/* Set PLL registers based on pixel clock rate*/
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if (pixclock > 65000000) {
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temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
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I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
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if (ret) {
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puts("I2C: failed to select dvi pll charge_cntl\n");
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return ret;
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}
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temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
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I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
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if (ret) {
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puts("I2C: failed to select dvi pll divider\n");
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return ret;
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}
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temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
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I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
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if (ret) {
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puts("I2C: failed to select dvi pll filter\n");
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return ret;
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}
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} else {
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temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
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I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
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if (ret) {
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puts("I2C: failed to select dvi pll charge_cntl\n");
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return ret;
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}
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temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
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I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
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if (ret) {
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puts("I2C: failed to select dvi pll divider\n");
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return ret;
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}
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temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
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I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
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if (ret) {
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puts("I2C: failed to select dvi pll filter\n");
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return ret;
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}
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}
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temp = I2C_DVI_POWER_MGMT_VAL;
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ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
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&temp, 1);
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if (ret) {
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puts("I2C: failed to select dvi power mgmt\n");
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return ret;
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}
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udelay(500);
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return 0;
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}
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