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https://github.com/brain-hackers/u-boot-brain
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caa7fc2c57
SPL is creating fit-images DT node when loadables are recorded in selected
configuration. Entries which are created are using entry-point and
load-addr property names. But there shouldn't be a need to use non standard
properties because entry/load are standard FIT properties. But using
standard FIT properties enables option to use generic FIT functions to
descrease SPL size. Here is result for ZynqMP virt configuration:
xilinx_zynqmp_virt: spl/u-boot-spl:all -82 spl/u-boot-spl:rodata -22 spl/u-boot-spl:text -60
The patch causes change in run time fit image record.
Before:
fit-images {
uboot {
os = "u-boot";
type = "firmware";
size = <0xfd520>;
entry-point = <0x8000000>;
load-addr = <0x8000000>;
};
};
After:
fit-images {
uboot {
os = "u-boot";
type = "firmware";
size = <0xfd520>;
entry = <0x8000000>;
load = <0x8000000>;
};
};
Replacing calling fdt_getprop_u32() by fit_image_get_entry/load() also
enables support for reading entry/load properties recorded in 64bit format.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| .. | ||
| beaglebone_vboot.txt | ||
| command_syntax_extensions.txt | ||
| howto.txt | ||
| kernel_fdt.its | ||
| kernel_fdts_compressed.its | ||
| kernel.its | ||
| multi_spl.its | ||
| multi-with-fpga.its | ||
| multi-with-loadables.its | ||
| multi.its | ||
| overlay-fdt-boot.txt | ||
| sec_firmware_ppa.its | ||
| sign-configs.its | ||
| sign-images.its | ||
| signature.txt | ||
| source_file_format.txt | ||
| uefi.its | ||
| update_uboot.its | ||
| update3.its | ||
| verified-boot.txt | ||
| x86-fit-boot.txt | ||