mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 00:48:52 +09:00
![Tom Rini](/assets/img/avatar_default.png)
In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
255 lines
4.9 KiB
C
255 lines
4.9 KiB
C
/*
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* SH SPI driver
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*
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* Copyright (C) 2011-2012 Renesas Solutions Corp.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <console.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/io.h>
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#include "sh_spi.h"
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static void sh_spi_write(unsigned long data, unsigned long *reg)
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{
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writel(data, reg);
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}
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static unsigned long sh_spi_read(unsigned long *reg)
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{
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return readl(reg);
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}
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static void sh_spi_set_bit(unsigned long val, unsigned long *reg)
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{
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unsigned long tmp;
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tmp = sh_spi_read(reg);
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tmp |= val;
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sh_spi_write(tmp, reg);
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}
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static void sh_spi_clear_bit(unsigned long val, unsigned long *reg)
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{
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unsigned long tmp;
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tmp = sh_spi_read(reg);
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tmp &= ~val;
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sh_spi_write(tmp, reg);
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}
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static void clear_fifo(struct sh_spi *ss)
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{
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sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2);
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sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2);
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}
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static int recvbuf_wait(struct sh_spi *ss)
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{
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while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) {
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if (ctrlc())
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return 1;
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udelay(10);
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}
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return 0;
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}
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static int write_fifo_empty_wait(struct sh_spi *ss)
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{
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while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) {
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if (ctrlc())
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return 1;
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udelay(10);
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}
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return 0;
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}
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void spi_init(void)
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{
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}
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static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
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{
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unsigned long val = 0;
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if (cs & 0x01)
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val |= SH_SPI_SSS0;
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if (cs & 0x02)
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val |= SH_SPI_SSS1;
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sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, &ss->regs->cr4);
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sh_spi_set_bit(val, &ss->regs->cr4);
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct sh_spi *ss;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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ss = spi_alloc_slave(struct sh_spi, bus, cs);
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if (!ss)
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return NULL;
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ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
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/* SPI sycle stop */
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sh_spi_write(0xfe, &ss->regs->cr1);
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/* CR1 init */
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sh_spi_write(0x00, &ss->regs->cr1);
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/* CR3 init */
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sh_spi_write(0x00, &ss->regs->cr3);
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sh_spi_set_cs(ss, cs);
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clear_fifo(ss);
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/* 1/8 clock */
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sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2);
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udelay(10);
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return &ss->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct sh_spi *spi = to_sh_spi(slave);
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free(spi);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct sh_spi *ss = to_sh_spi(slave);
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sh_spi_write(sh_spi_read(&ss->regs->cr1) &
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~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), &ss->regs->cr1);
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}
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static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data,
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unsigned int len, unsigned long flags)
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{
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int i, cur_len, ret = 0;
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int remain = (int)len;
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if (len >= SH_SPI_FIFO_SIZE)
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sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
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while (remain > 0) {
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cur_len = (remain < SH_SPI_FIFO_SIZE) ?
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remain : SH_SPI_FIFO_SIZE;
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for (i = 0; i < cur_len &&
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!(sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) &&
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!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBF);
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i++)
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sh_spi_write(tx_data[i], &ss->regs->tbr_rbr);
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cur_len = i;
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if (sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) {
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/* Abort the transaction */
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flags |= SPI_XFER_END;
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sh_spi_set_bit(SH_SPI_WPABRT, &ss->regs->cr4);
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ret = 1;
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break;
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}
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remain -= cur_len;
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tx_data += cur_len;
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if (remain > 0)
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write_fifo_empty_wait(ss);
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}
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if (flags & SPI_XFER_END) {
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sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
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sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
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udelay(100);
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write_fifo_empty_wait(ss);
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}
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return ret;
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}
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static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data,
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unsigned int len, unsigned long flags)
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{
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int i;
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if (len > SH_SPI_MAX_BYTE)
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sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3);
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else
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sh_spi_write(len, &ss->regs->cr3);
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sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
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sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
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for (i = 0; i < len; i++) {
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if (recvbuf_wait(ss))
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return 0;
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rx_data[i] = (unsigned char)sh_spi_read(&ss->regs->tbr_rbr);
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}
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sh_spi_write(0, &ss->regs->cr3);
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return 0;
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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struct sh_spi *ss = to_sh_spi(slave);
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const unsigned char *tx_data = dout;
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unsigned char *rx_data = din;
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unsigned int len = bitlen / 8;
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int ret = 0;
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if (flags & SPI_XFER_BEGIN)
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sh_spi_write(sh_spi_read(&ss->regs->cr1) & ~SH_SPI_SSA,
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&ss->regs->cr1);
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if (tx_data)
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ret = sh_spi_send(ss, tx_data, len, flags);
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if (ret == 0 && rx_data)
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ret = sh_spi_receive(ss, rx_data, len, flags);
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if (flags & SPI_XFER_END) {
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sh_spi_set_bit(SH_SPI_SSD, &ss->regs->cr1);
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udelay(100);
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sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD,
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&ss->regs->cr1);
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clear_fifo(ss);
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}
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return ret;
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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if (!bus && cs < SH_SPI_NUM_CS)
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return 1;
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else
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return 0;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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}
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