mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
e895a4b06f
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
158 lines
3.2 KiB
C
158 lines
3.2 KiB
C
/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
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*
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* Author: Scott Wood <scottwood@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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#include <pci.h>
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#include <mpc83xx.h>
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#include <vsc7385.h>
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#include <ns16550.h>
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#include <nand.h>
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#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
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#include <asm/gpio.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
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gd->flags |= GD_FLG_SILENT;
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#endif
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#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
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mpc83xx_gpio_init_f();
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#endif
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return 0;
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}
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int board_early_init_r(void)
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{
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#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
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mpc83xx_gpio_init_r();
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#endif
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: Freescale MPC8313ERDB\n");
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return 0;
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}
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#ifndef CONFIG_SPL_BUILD
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static struct pci_region pci_regions[] = {
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{
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.bus_start = CONFIG_SYS_PCI1_MEM_BASE,
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.phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
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.size = CONFIG_SYS_PCI1_MEM_SIZE,
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.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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.bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
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.phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
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.size = CONFIG_SYS_PCI1_MMIO_SIZE,
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.flags = PCI_REGION_MEM
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},
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{
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.bus_start = CONFIG_SYS_PCI1_IO_BASE,
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.phys_start = CONFIG_SYS_PCI1_IO_PHYS,
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.size = CONFIG_SYS_PCI1_IO_SIZE,
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.flags = PCI_REGION_IO
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}
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};
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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struct pci_region *reg[] = { pci_regions };
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/* Enable all 3 PCI_CLK_OUTPUTs. */
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clk->occr |= 0xe0000000;
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/*
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* Configure PCI Local Access Windows
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*/
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pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
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pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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mpc83xx_pci_init(1, reg);
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}
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/*
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* Miscellaneous late-boot configurations
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*
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* If a VSC7385 microcode image is present, then upload it.
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*/
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int misc_init_r(void)
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{
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int rc = 0;
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#ifdef CONFIG_VSC7385_IMAGE
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if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
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CONFIG_VSC7385_IMAGE_SIZE)) {
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puts("Failure uploading VSC7385 microcode.\n");
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rc = 1;
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}
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#endif
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return rc;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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return 0;
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}
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#endif
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#else /* CONFIG_SPL_BUILD */
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void board_init_f(ulong bootflag)
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{
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board_early_init_f();
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NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
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CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
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puts("NAND boot... ");
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init_timebase();
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initdram(0);
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relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
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CONFIG_SYS_NAND_U_BOOT_RELOC);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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nand_boot();
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}
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void putc(char c)
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{
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if (gd->flags & GD_FLG_SILENT)
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return;
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if (c == '\n')
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NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
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NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
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}
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#endif
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