mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 08:28:51 +09:00
![wdenk](/assets/img/avatar_default.png)
before we can access it; add delay in case we are faster (with no CF card inserted) * Cleanup of some init functions * Make sure SCC Ethernet is always stopped by the time we boot Linux to avoid Linux crashes by early packets coming in. * Accelerate flash accesses on LWMON board by using buffered writes
225 lines
5.3 KiB
C
225 lines
5.3 KiB
C
/*
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* (C) Copyright 2001
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include "dasa_sim.h"
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/* ------------------------------------------------------------------------- */
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#undef FPGA_DEBUG
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#define _NOT_USED_ 0xFFFFFFFF
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/* ------------------------------------------------------------------------- */
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/* fpga configuration data - generated by bit2inc */
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static unsigned char fpgadata[] = {
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#include "fpgadata.c"
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};
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#define FPGA_PRG_SLEEP 32 /* fpga program sleep-time */
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#define LOAD_LONG(a) a
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/******************************************************************************
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*
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* sysFpgaBoot - Load fpga-image into fpga
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*
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*/
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static int fpgaBoot (void)
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{
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int i, j, index, len;
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unsigned char b;
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int imageSize;
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imageSize = sizeof (fpgadata);
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpgadata[index];
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index += len + 3;
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}
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/* search for preamble 0xFF2X */
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for (index = 0; index < imageSize - 1; index++) {
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if ((fpgadata[index] == 0xff)
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&& ((fpgadata[index + 1] & 0xf0) == 0x20))
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break;
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}
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/* enable cs1 instead of user0... */
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*(unsigned long *) 0x50000084 &= ~0x00000002;
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#ifdef FPGA_DEBUG
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printf ("%s\n",
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((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE");
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#endif
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/* init fpga by asserting and deasserting PROGRAM* (USER2)... */
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*(unsigned long *) 0x50000084 &= ~0x00000400;
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udelay (FPGA_PRG_SLEEP * 1000);
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*(unsigned long *) 0x50000084 |= 0x00000400;
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udelay (FPGA_PRG_SLEEP * 1000);
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#ifdef FPGA_DEBUG
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printf ("%s\n",
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((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE");
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#endif
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/* cs1: disable burst, disable ready */
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*(unsigned long *) 0x50000114 &= ~0x00000300;
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/* cs1: set write timing */
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*(unsigned long *) 0x50000118 |= 0x00010900;
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/* write configuration-data into fpga... */
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for (i = index; i < imageSize; i++) {
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b = fpgadata[i];
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for (j = 0; j < 8; j++) {
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*(unsigned long *) 0x30000000 =
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((b & 0x80) == 0x80)
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? LOAD_LONG (0x03030101)
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: LOAD_LONG (0x02020000);
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b <<= 1;
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}
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}
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#ifdef FPGA_DEBUG
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printf ("%s\n",
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((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE");
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#endif
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/* set cs1 to 32 bit data-width, disable burst, enable ready */
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*(unsigned long *) 0x50000114 |= 0x00000202;
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*(unsigned long *) 0x50000114 &= ~0x00000100;
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/* cs1: set iop access to little endian */
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*(unsigned long *) 0x50000114 &= ~0x00000010;
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/* cs1: set read and write timing */
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*(unsigned long *) 0x50000118 = 0x00010000;
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*(unsigned long *) 0x5000011c = 0x00010001;
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#ifdef FPGA_DEBUG
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printf ("%s\n",
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((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE");
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#endif
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/* wait for 30 ms... */
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udelay (30 * 1000);
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/* check if fpga's DONE signal - correctly booted ? */
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if ((*(unsigned long *) 0x50000084 & 0x00010000) == 0)
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return -1;
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return 0;
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}
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int board_early_init_f (void)
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{
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/*
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* Init pci regs
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*/
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*(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */
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*(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */
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*(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */
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*(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */
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*(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */
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*(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */
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*(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */
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return 0;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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int index;
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int len;
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unsigned char str[64];
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int i = getenv_r ("serial#", str, sizeof (str));
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int fpga;
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unsigned short val;
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puts ("Board: ");
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/*
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* Boot onboard FPGA
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*/
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fpga = fpgaBoot ();
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if (!i || strncmp (str, "DASA_SIM", 8)) {
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puts ("### No HW ID - assuming DASA_SIM");
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}
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puts (str);
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if (fpga == 0) {
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val = *(unsigned short *) 0x30000202;
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printf (" (Id=%d Version=%d Revision=%d)",
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(val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1);
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puts ("\nFPGA: ");
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpgadata[index];
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printf ("%s ", &(fpgadata[index + 1]));
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index += len + 3;
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}
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} else {
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puts ("\nFPGA: Booting failed!");
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}
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putc ('\n');
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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return (16 * 1024 * 1024);
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 16 MB - ok\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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