brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-07-25 20:39:43 +09:00
Code Issues Projects Releases Wiki Activity
207774b213
u-boot-brain/arch/arm/cpu/armv8/fsl-lsch3
History
York Sun 207774b213 armv8/ls2085a: Fix generic timer clock source 
The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Mark Rutland <mark.rutland@arm.com>
2015-04-23 08:55:55 -07:00
..
cpu.c armv8/ls2085a: Fix generic timer clock source 2015-04-23 08:55:55 -07:00
cpu.h armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page 2014-09-25 08:36:19 -07:00
fdt.c armv8/fsl-lsch3: Add fdt-fixup for clock frequency of the DUART nodes 2015-02-24 13:08:53 -08:00
lowlevel.S armv8/ls2085a: Fix generic timer clock source 2015-04-23 08:55:55 -07:00
Makefile armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page 2014-09-25 08:36:19 -07:00
mp.c armv8/ls2085a: Fix generic timer clock source 2015-04-23 08:55:55 -07:00
mp.h armv8/ls2085a: Fix generic timer clock source 2015-04-23 08:55:55 -07:00
README fsl-ch3/README: Add description for NOR flash layout (firmware images) 2015-04-21 10:27:07 -07:00
speed.c armv8/fsl-lsch3: Fix platform clock calculation 2015-04-23 08:55:55 -07:00
speed.h ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC 2014-07-03 08:40:51 +02:00

README 

#
# Copyright 2014 Freescale Semiconductor
#
# SPDX-License-Identifier:      GPL-2.0+
#

Freescale LayerScape with Chassis Generation 3

This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
for example LS2085A.

Flash Layout
============
A typical layout of various images (including Linux and other firmware images)
is shown below considering a 32MB NOR flash device:

	-------------------------
	|	linux		|
	------------------------- ----> 0x0120_0000
	|	Debug Server 	|
	------------------------- ----> 0x00C0_0000
	|	AIOP SW 	|
	------------------------- ----> 0x0070_0000
	|	MC FW 		|
	------------------------- ----> 0x006C_0000
	| MC Data Path Layout 	|
	------------------------- ----> 0x0020_0000
	|	BootLoader 	|
	------------------------- ----> 0x0000_1000
	|	PBI 		|
	------------------------- ----> 0x0000_0080
	|	RCW 		|
	------------------------- ----> 0x0000_0000

	32-MB NOR flash layout