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https://github.com/brain-hackers/u-boot-brain
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![Stefan Mavrodiev](/assets/img/avatar_default.png)
Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is adapted from mailine kernel. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
457 lines
10 KiB
C
457 lines
10 KiB
C
/*
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* (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
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* S.J.R. van Schaik <stephan@whiteboxsystems.nl>
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* M.B.W. Wajer <merlijn@whiteboxsystems.nl>
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*
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* (C) Copyright 2017 Olimex Ltd..
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* Stefan Mavrodiev <stefan@olimex.com>
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*
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* Based on linux spi driver. Original copyright follows:
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* linux/drivers/spi/spi-sun4i.c
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*
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* Copyright (C) 2012 - 2014 Allwinner Tech
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* Pan Nan <pannan@allwinnertech.com>
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*
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* Copyright (C) 2014 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <spi.h>
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#include <errno.h>
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#include <fdt_support.h>
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#include <wait_bit.h>
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#include <asm/bitops.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#define SUN4I_FIFO_DEPTH 64
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#define SUN4I_RXDATA_REG 0x00
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#define SUN4I_TXDATA_REG 0x04
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#define SUN4I_CTL_REG 0x08
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#define SUN4I_CTL_ENABLE BIT(0)
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#define SUN4I_CTL_MASTER BIT(1)
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#define SUN4I_CTL_CPHA BIT(2)
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#define SUN4I_CTL_CPOL BIT(3)
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#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4)
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#define SUN4I_CTL_LMTF BIT(6)
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#define SUN4I_CTL_TF_RST BIT(8)
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#define SUN4I_CTL_RF_RST BIT(9)
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#define SUN4I_CTL_XCH_MASK 0x0400
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#define SUN4I_CTL_XCH BIT(10)
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#define SUN4I_CTL_CS_MASK 0x3000
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#define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK)
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#define SUN4I_CTL_DHB BIT(15)
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#define SUN4I_CTL_CS_MANUAL BIT(16)
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#define SUN4I_CTL_CS_LEVEL BIT(17)
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#define SUN4I_CTL_TP BIT(18)
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#define SUN4I_INT_CTL_REG 0x0c
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#define SUN4I_INT_CTL_RF_F34 BIT(4)
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#define SUN4I_INT_CTL_TF_E34 BIT(12)
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#define SUN4I_INT_CTL_TC BIT(16)
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#define SUN4I_INT_STA_REG 0x10
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#define SUN4I_DMA_CTL_REG 0x14
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#define SUN4I_WAIT_REG 0x18
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#define SUN4I_CLK_CTL_REG 0x1c
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#define SUN4I_CLK_CTL_CDR2_MASK 0xff
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#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
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#define SUN4I_CLK_CTL_CDR1_MASK 0xf
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#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
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#define SUN4I_CLK_CTL_DRS BIT(12)
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#define SUN4I_MAX_XFER_SIZE 0xffffff
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#define SUN4I_BURST_CNT_REG 0x20
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#define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
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#define SUN4I_XMIT_CNT_REG 0x24
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#define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
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#define SUN4I_FIFO_STA_REG 0x28
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#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
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#define SUN4I_FIFO_STA_RF_CNT_BITS 0
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#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
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#define SUN4I_FIFO_STA_TF_CNT_BITS 16
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#define SUN4I_SPI_MAX_RATE 24000000
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#define SUN4I_SPI_MIN_RATE 3000
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#define SUN4I_SPI_DEFAULT_RATE 1000000
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#define SUN4I_SPI_TIMEOUT_US 1000000
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/* sun4i spi register set */
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struct sun4i_spi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctl;
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u32 intctl;
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u32 st;
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u32 dmactl;
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u32 wait;
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u32 cctl;
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u32 bc;
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u32 tc;
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u32 fifo_sta;
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};
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struct sun4i_spi_platdata {
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u32 base_addr;
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u32 max_hz;
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};
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struct sun4i_spi_priv {
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struct sun4i_spi_regs *regs;
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u32 freq;
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u32 mode;
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const u8 *tx_buf;
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u8 *rx_buf;
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};
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DECLARE_GLOBAL_DATA_PTR;
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static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
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{
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u8 byte;
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while (len--) {
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byte = readb(&priv->regs->rxdata);
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*priv->rx_buf++ = byte;
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}
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}
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static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len)
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{
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u8 byte;
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while (len--) {
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byte = priv->tx_buf ? *priv->tx_buf++ : 0;
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writeb(byte, &priv->regs->txdata);
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}
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}
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static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
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{
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struct sun4i_spi_priv *priv = dev_get_priv(bus);
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u32 reg;
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reg = readl(&priv->regs->ctl);
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reg &= ~SUN4I_CTL_CS_MASK;
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reg |= SUN4I_CTL_CS(cs);
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if (enable)
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reg &= ~SUN4I_CTL_CS_LEVEL;
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else
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reg |= SUN4I_CTL_CS_LEVEL;
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writel(reg, &priv->regs->ctl);
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}
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static int sun4i_spi_parse_pins(struct udevice *dev)
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{
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const void *fdt = gd->fdt_blob;
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const char *pin_name;
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const fdt32_t *list;
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u32 phandle;
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int drive, pull = 0, pin, i;
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int offset;
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int size;
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list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size);
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if (!list) {
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printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n");
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return -EINVAL;
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}
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while (size) {
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phandle = fdt32_to_cpu(*list++);
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size -= sizeof(*list);
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offset = fdt_node_offset_by_phandle(fdt, phandle);
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if (offset < 0)
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return offset;
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drive = fdt_getprop_u32_default_node(fdt, offset, 0,
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"drive-strength", 0);
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if (drive) {
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if (drive <= 10)
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drive = 0;
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else if (drive <= 20)
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drive = 1;
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else if (drive <= 30)
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drive = 2;
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else
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drive = 3;
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} else {
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drive = fdt_getprop_u32_default_node(fdt, offset, 0,
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"allwinner,drive",
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0);
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drive = min(drive, 3);
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}
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if (fdt_get_property(fdt, offset, "bias-disable", NULL))
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pull = 0;
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else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL))
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pull = 1;
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else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL))
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pull = 2;
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else
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pull = fdt_getprop_u32_default_node(fdt, offset, 0,
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"allwinner,pull",
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0);
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pull = min(pull, 2);
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for (i = 0; ; i++) {
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pin_name = fdt_stringlist_get(fdt, offset,
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"pins", i, NULL);
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if (!pin_name) {
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pin_name = fdt_stringlist_get(fdt, offset,
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"allwinner,pins",
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i, NULL);
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if (!pin_name)
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break;
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}
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pin = name_to_gpio(pin_name);
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if (pin < 0)
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break;
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
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sunxi_gpio_set_drv(pin, drive);
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sunxi_gpio_set_pull(pin, pull);
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}
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}
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return 0;
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}
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static inline void sun4i_spi_enable_clock(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *const)SUNXI_CCM_BASE;
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setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0));
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writel((1 << 31), &ccm->spi0_clk_cfg);
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}
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static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
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int node = dev_of_offset(bus);
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plat->base_addr = devfdt_get_addr(bus);
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plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
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"spi-max-frequency",
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SUN4I_SPI_DEFAULT_RATE);
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if (plat->max_hz > SUN4I_SPI_MAX_RATE)
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plat->max_hz = SUN4I_SPI_MAX_RATE;
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return 0;
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}
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static int sun4i_spi_probe(struct udevice *bus)
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{
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struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
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struct sun4i_spi_priv *priv = dev_get_priv(bus);
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sun4i_spi_enable_clock();
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sun4i_spi_parse_pins(bus);
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priv->regs = (struct sun4i_spi_regs *)(uintptr_t)plat->base_addr;
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priv->freq = plat->max_hz;
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return 0;
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}
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static int sun4i_spi_claim_bus(struct udevice *dev)
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{
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struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
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writel(SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP |
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SUN4I_CTL_CS_MANUAL | SUN4I_CTL_CS_ACTIVE_LOW,
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&priv->regs->ctl);
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return 0;
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}
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static int sun4i_spi_release_bus(struct udevice *dev)
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{
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struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
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u32 reg;
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reg = readl(&priv->regs->ctl);
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reg &= ~SUN4I_CTL_ENABLE;
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writel(reg, &priv->regs->ctl);
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return 0;
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}
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static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct sun4i_spi_priv *priv = dev_get_priv(bus);
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struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
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u32 len = bitlen / 8;
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u32 reg;
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u8 nbytes;
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int ret;
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priv->tx_buf = dout;
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priv->rx_buf = din;
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if (bitlen % 8) {
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debug("%s: non byte-aligned SPI transfer.\n", __func__);
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return -ENAVAIL;
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}
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if (flags & SPI_XFER_BEGIN)
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sun4i_spi_set_cs(bus, slave_plat->cs, true);
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reg = readl(&priv->regs->ctl);
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/* Reset FIFOs */
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writel(reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST, &priv->regs->ctl);
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while (len) {
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/* Setup the transfer now... */
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nbytes = min(len, (u32)(SUN4I_FIFO_DEPTH - 1));
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/* Setup the counters */
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writel(SUN4I_BURST_CNT(nbytes), &priv->regs->bc);
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writel(SUN4I_XMIT_CNT(nbytes), &priv->regs->tc);
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/* Fill the TX FIFO */
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sun4i_spi_fill_fifo(priv, nbytes);
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/* Start the transfer */
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reg = readl(&priv->regs->ctl);
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writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl);
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/* Wait transfer to complete */
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ret = wait_for_bit_le32(&priv->regs->ctl, SUN4I_CTL_XCH_MASK,
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false, SUN4I_SPI_TIMEOUT_US, false);
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if (ret) {
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printf("ERROR: sun4i_spi: Timeout transferring data\n");
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sun4i_spi_set_cs(bus, slave_plat->cs, false);
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return ret;
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}
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/* Drain the RX FIFO */
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sun4i_spi_drain_fifo(priv, nbytes);
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len -= nbytes;
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}
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if (flags & SPI_XFER_END)
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sun4i_spi_set_cs(bus, slave_plat->cs, false);
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return 0;
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}
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static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
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{
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struct sun4i_spi_platdata *plat = dev_get_platdata(dev);
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struct sun4i_spi_priv *priv = dev_get_priv(dev);
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unsigned int div;
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u32 reg;
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if (speed > plat->max_hz)
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speed = plat->max_hz;
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if (speed < SUN4I_SPI_MIN_RATE)
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speed = SUN4I_SPI_MIN_RATE;
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/*
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* Setup clock divider.
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*
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* We have two choices there. Either we can use the clock
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* divide rate 1, which is calculated thanks to this formula:
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* SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
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* Or we can use CDR2, which is calculated with the formula:
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* SPI_CLK = MOD_CLK / (2 * (cdr + 1))
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* Whether we use the former or the latter is set through the
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* DRS bit.
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*
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* First try CDR2, and if we can't reach the expected
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* frequency, fall back to CDR1.
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*/
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div = SUN4I_SPI_MAX_RATE / (2 * speed);
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reg = readl(&priv->regs->cctl);
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if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
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if (div > 0)
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div--;
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reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
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reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
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} else {
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div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed);
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reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
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reg |= SUN4I_CLK_CTL_CDR1(div);
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}
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priv->freq = speed;
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writel(reg, &priv->regs->cctl);
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return 0;
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}
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static int sun4i_spi_set_mode(struct udevice *dev, uint mode)
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{
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struct sun4i_spi_priv *priv = dev_get_priv(dev);
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u32 reg;
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reg = readl(&priv->regs->ctl);
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reg &= ~(SUN4I_CTL_CPOL | SUN4I_CTL_CPHA);
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if (mode & SPI_CPOL)
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reg |= SUN4I_CTL_CPOL;
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if (mode & SPI_CPHA)
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reg |= SUN4I_CTL_CPHA;
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priv->mode = mode;
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writel(reg, &priv->regs->ctl);
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return 0;
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}
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static const struct dm_spi_ops sun4i_spi_ops = {
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.claim_bus = sun4i_spi_claim_bus,
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.release_bus = sun4i_spi_release_bus,
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.xfer = sun4i_spi_xfer,
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.set_speed = sun4i_spi_set_speed,
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.set_mode = sun4i_spi_set_mode,
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};
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static const struct udevice_id sun4i_spi_ids[] = {
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{ .compatible = "allwinner,sun4i-a10-spi" },
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{ }
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};
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U_BOOT_DRIVER(sun4i_spi) = {
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.name = "sun4i_spi",
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.id = UCLASS_SPI,
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.of_match = sun4i_spi_ids,
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.ops = &sun4i_spi_ops,
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.ofdata_to_platdata = sun4i_spi_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct sun4i_spi_platdata),
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.priv_auto_alloc_size = sizeof(struct sun4i_spi_priv),
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.probe = sun4i_spi_probe,
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};
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