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https://github.com/brain-hackers/u-boot-brain
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afabb498b7
This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. As a part from this cleanup, the GPIO definitions for PPC405EP are corrected. The high and low parts of the registers (for example CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in the wrong order. This patch now fixes this issue by switching these xxxH and xxxL values. This brings the GPIO 405EP port in sync with all other PPC4xx ports. Signed-off-by: Stefan Roese <sr@denx.de>
81 lines
3.5 KiB
C
81 lines
3.5 KiB
C
/*----------------------------------------------------------------------------+
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| This source code is dual-licensed. You may use it under the terms of the
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| GNU General Public License version 2, or under the license below.
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| This source code has been made available to you by IBM on an AS-IS
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| basis. Anyone receiving this source is licensed under IBM
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| copyrights to use it in any way he or she deems fit, including
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| copying it, modifying it, compiling it, and redistributing it either
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| with or without modifications. No license under IBM patents or
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| patent applications is to be implied by the copyright license.
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| Any user of this software should understand that IBM cannot provide
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| technical support for this software and will not be responsible for
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| any consequences resulting from the use of this software.
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| Any person who transfers this source code or any derivative work
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| must include the IBM copyright notice, this paragraph, and the
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| preceding two paragraphs in the transferred software.
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| COPYRIGHT I B M CORPORATION 1999
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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+----------------------------------------------------------------------------*/
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#ifndef __PPC405_H__
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#define __PPC405_H__
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/* Define bits and masks for real-mode storage attribute control registers */
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#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
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#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
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#ifndef CONFIG_IOP480
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#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
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#else
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#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480(403)*/
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#endif
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/* DCR registers */
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#define PLB0_ACR 0x0087
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/* SDR registers */
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#define SDR0_PINSTP 0x0040
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/* CPR registers */
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#define CPR0_CLKUPD 0x0020
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#define CPR0_PLLC 0x0040
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#define CPR0_PLLD 0x0060
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#define CPR0_CPUD 0x0080
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#define CPR0_PLBD 0x00a0
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#define CPR0_OPBD0 0x00c0
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#define CPR0_PERD 0x00e0
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/*
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* DMA
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*/
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#define DMA_DCR_BASE 0x0100
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#define DMACR0 (DMA_DCR_BASE + 0x00) /* DMA channel control reg 0 */
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#define DMACT0 (DMA_DCR_BASE + 0x01) /* DMA count reg 0 */
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#define DMADA0 (DMA_DCR_BASE + 0x02) /* DMA destination address reg 0 */
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#define DMASA0 (DMA_DCR_BASE + 0x03) /* DMA source address reg 0 */
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#define DMASB0 (DMA_DCR_BASE + 0x04) /* DMA sg descriptor addr 0 */
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#define DMACR1 (DMA_DCR_BASE + 0x08) /* DMA channel control reg 1 */
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#define DMACT1 (DMA_DCR_BASE + 0x09) /* DMA count reg 1 */
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#define DMADA1 (DMA_DCR_BASE + 0x0a) /* DMA destination address reg 1 */
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#define DMASA1 (DMA_DCR_BASE + 0x0b) /* DMA source address reg 1 */
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#define DMASB1 (DMA_DCR_BASE + 0x0c) /* DMA sg descriptor addr 1 */
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#define DMACR2 (DMA_DCR_BASE + 0x10) /* DMA channel control reg 2 */
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#define DMACT2 (DMA_DCR_BASE + 0x11) /* DMA count reg 2 */
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#define DMADA2 (DMA_DCR_BASE + 0x12) /* DMA destination address reg 2 */
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#define DMASA2 (DMA_DCR_BASE + 0x13) /* DMA source address reg 2 */
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#define DMASB2 (DMA_DCR_BASE + 0x14) /* DMA sg descriptor addr 2 */
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#define DMACR3 (DMA_DCR_BASE + 0x18) /* DMA channel control reg 3 */
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#define DMACT3 (DMA_DCR_BASE + 0x19) /* DMA count reg 3 */
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#define DMADA3 (DMA_DCR_BASE + 0x1a) /* DMA destination address reg 3 */
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#define DMASA3 (DMA_DCR_BASE + 0x1b) /* DMA source address reg 3 */
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#define DMASB3 (DMA_DCR_BASE + 0x1c) /* DMA sg descriptor addr 3 */
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#define DMASR (DMA_DCR_BASE + 0x20) /* DMA status reg */
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#define DMASGC (DMA_DCR_BASE + 0x23) /* DMA scatter/gather command reg*/
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#define DMAADR (DMA_DCR_BASE + 0x24) /* DMA address decode reg */
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#endif /* __PPC405_H__ */
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