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https://github.com/brain-hackers/u-boot-brain
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fbb0de088b
This patch makes sure that the flush/invalidate_dcache_range() functions can handle corner-case calls like this -- invalidate_dcache_range(0, 0, 0); This call is valid and is happily produced by USB EHCI code for example. The expected behavior of the cache function(s) in this case is that they will do no operation, since the size is zero. The current implementation though has a problem where such invocation will result in a hard CPU hang. This is because under such conditions, where the start_addr = 0 and stop = 0, the addr = 0 and aend = 0xffffffe0 . The loop will then try to iterate over the entire address space, which in itself is wrong. But iterating over the entire address space might also hit some odd address which will cause bus hang. The later happens on the Atheros MIPS. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Hans de Goede <hdegoede@redhat.com>
127 lines
2.7 KiB
C
127 lines
2.7 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/cacheops.h>
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#include <asm/mipsregs.h>
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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static inline unsigned long icache_line_size(void)
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{
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return CONFIG_SYS_CACHELINE_SIZE;
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}
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static inline unsigned long dcache_line_size(void)
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{
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return CONFIG_SYS_CACHELINE_SIZE;
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}
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#else /* !CONFIG_SYS_CACHELINE_SIZE */
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static inline unsigned long icache_line_size(void)
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{
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unsigned long conf1, il;
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conf1 = read_c0_config1();
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il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
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if (!il)
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return 0;
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return 2 << il;
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}
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static inline unsigned long dcache_line_size(void)
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{
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unsigned long conf1, dl;
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conf1 = read_c0_config1();
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dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
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if (!dl)
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return 0;
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return 2 << dl;
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}
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#endif /* !CONFIG_SYS_CACHELINE_SIZE */
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void flush_cache(ulong start_addr, ulong size)
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{
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unsigned long ilsize = icache_line_size();
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unsigned long dlsize = dcache_line_size();
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const void *addr, *aend;
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/* aend will be miscalculated when size is zero, so we return here */
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if (size == 0)
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return;
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addr = (const void *)(start_addr & ~(dlsize - 1));
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aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1));
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if (ilsize == dlsize) {
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/* flush I-cache & D-cache simultaneously */
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while (1) {
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mips_cache(HIT_WRITEBACK_INV_D, addr);
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mips_cache(HIT_INVALIDATE_I, addr);
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if (addr == aend)
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break;
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addr += dlsize;
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}
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return;
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}
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/* flush D-cache */
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while (1) {
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mips_cache(HIT_WRITEBACK_INV_D, addr);
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if (addr == aend)
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break;
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addr += dlsize;
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}
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/* flush I-cache */
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addr = (const void *)(start_addr & ~(ilsize - 1));
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aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1));
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while (1) {
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mips_cache(HIT_INVALIDATE_I, addr);
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if (addr == aend)
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break;
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addr += ilsize;
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}
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}
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void flush_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = dcache_line_size();
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const void *addr = (const void *)(start_addr & ~(lsize - 1));
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const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
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/* aend will be miscalculated when size is zero, so we return here */
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if (start_addr == stop)
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return;
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while (1) {
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mips_cache(HIT_WRITEBACK_INV_D, addr);
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if (addr == aend)
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break;
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addr += lsize;
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}
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}
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void invalidate_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = dcache_line_size();
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const void *addr = (const void *)(start_addr & ~(lsize - 1));
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const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
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/* aend will be miscalculated when size is zero, so we return here */
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if (start_addr == stop)
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return;
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while (1) {
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mips_cache(HIT_INVALIDATE_D, addr);
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if (addr == aend)
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break;
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addr += lsize;
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}
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}
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