mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-10 04:03:46 +09:00
25ab4b0303
Rather than assuming that the chip offset length is 1, allow it to be provided. This allows chips that don't use the default offset length to be used (at present they are only supported by the command line 'i2c' command which sets the offset length explicitly). Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
66 lines
1.6 KiB
C
66 lines
1.6 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <tps6586x.h>
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#include <asm/io.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/tegra_i2c.h>
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#include <asm/arch-tegra/sys_proto.h>
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#define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */
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#define VDD_CPU_NOMINAL_T25 0x10 /* 1.125v */
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#define VDD_CORE_NOMINAL_T20 0x16 /* 1.275v */
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#define VDD_CPU_NOMINAL_T20 0x0f /* 1.1v */
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#define VDD_RELATION 0x02 /* 50mv */
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#define VDD_TRANSITION_STEP 0x06 /* 150mv */
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#define VDD_TRANSITION_RATE 0x06 /* 3.52mv/us */
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#define PMI_I2C_ADDRESS 0x34 /* chip requires this address */
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int pmu_set_nominal(void)
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{
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struct udevice *bus, *dev;
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int core, cpu;
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int ret;
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/* by default, the table has been filled with T25 settings */
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switch (tegra_get_chip_sku()) {
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case TEGRA_SOC_T20:
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core = VDD_CORE_NOMINAL_T20;
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cpu = VDD_CPU_NOMINAL_T20;
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break;
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case TEGRA_SOC_T25:
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core = VDD_CORE_NOMINAL_T25;
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cpu = VDD_CPU_NOMINAL_T25;
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break;
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default:
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debug("%s: Unknown SKU id\n", __func__);
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return -1;
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}
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ret = tegra_i2c_get_dvc_bus(&bus);
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if (ret) {
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debug("%s: Cannot find DVC I2C bus\n", __func__);
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return ret;
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}
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ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, 1, &dev);
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if (ret) {
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debug("%s: Cannot find DVC I2C chip\n", __func__);
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return ret;
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}
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tps6586x_init(dev);
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tps6586x_set_pwm_mode(TPS6586X_PWM_SM1);
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return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP,
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VDD_TRANSITION_RATE, VDD_RELATION);
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}
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