mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
29af2ac48c
There is no reason to have firmware specific structure in clock driver. Move it to generic location and also initialize enum values which is based on https://lore.kernel.org/linux-arm-kernel/20200318125003.GA2727094@kroah.com/ recommended way to go to make sure that values guaranteed by compiler. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
112 lines
2.7 KiB
C
112 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Xilinx Zynq MPSoC Firmware driver
|
|
*
|
|
* Copyright (C) 2018-2019 Xilinx, Inc.
|
|
*/
|
|
|
|
#ifndef _ZYNQMP_FIRMWARE_H_
|
|
#define _ZYNQMP_FIRMWARE_H_
|
|
|
|
enum pm_api_id {
|
|
PM_GET_API_VERSION = 1,
|
|
PM_SET_CONFIGURATION,
|
|
PM_GET_NODE_STATUS,
|
|
PM_GET_OPERATING_CHARACTERISTIC,
|
|
PM_REGISTER_NOTIFIER,
|
|
PM_REQUEST_SUSPEND,
|
|
PM_SELF_SUSPEND,
|
|
PM_FORCE_POWERDOWN,
|
|
PM_ABORT_SUSPEND,
|
|
PM_REQUEST_WAKEUP,
|
|
PM_SET_WAKEUP_SOURCE,
|
|
PM_SYSTEM_SHUTDOWN,
|
|
PM_REQUEST_NODE,
|
|
PM_RELEASE_NODE,
|
|
PM_SET_REQUIREMENT,
|
|
PM_SET_MAX_LATENCY,
|
|
PM_RESET_ASSERT,
|
|
PM_RESET_GET_STATUS,
|
|
PM_MMIO_WRITE,
|
|
PM_MMIO_READ,
|
|
PM_PM_INIT_FINALIZE,
|
|
PM_FPGA_LOAD,
|
|
PM_FPGA_GET_STATUS,
|
|
PM_GET_CHIPID,
|
|
PM_SECURE_SHA = 26,
|
|
PM_SECURE_RSA,
|
|
PM_PINCTRL_REQUEST,
|
|
PM_PINCTRL_RELEASE,
|
|
PM_PINCTRL_GET_FUNCTION,
|
|
PM_PINCTRL_SET_FUNCTION,
|
|
PM_PINCTRL_CONFIG_PARAM_GET,
|
|
PM_PINCTRL_CONFIG_PARAM_SET,
|
|
PM_IOCTL,
|
|
PM_QUERY_DATA,
|
|
PM_CLOCK_ENABLE,
|
|
PM_CLOCK_DISABLE,
|
|
PM_CLOCK_GETSTATE,
|
|
PM_CLOCK_SETDIVIDER,
|
|
PM_CLOCK_GETDIVIDER,
|
|
PM_CLOCK_SETRATE,
|
|
PM_CLOCK_GETRATE,
|
|
PM_CLOCK_SETPARENT,
|
|
PM_CLOCK_GETPARENT,
|
|
PM_SECURE_IMAGE,
|
|
PM_FPGA_READ = 46,
|
|
PM_SECURE_AES,
|
|
PM_CLOCK_PLL_GETPARAM = 49,
|
|
PM_REGISTER_ACCESS = 52,
|
|
PM_EFUSE_ACCESS,
|
|
PM_FEATURE_CHECK = 63,
|
|
PM_API_MAX,
|
|
};
|
|
|
|
enum pm_query_id {
|
|
PM_QID_INVALID = 0,
|
|
PM_QID_CLOCK_GET_NAME = 1,
|
|
PM_QID_CLOCK_GET_TOPOLOGY = 2,
|
|
PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
|
|
PM_QID_CLOCK_GET_PARENTS = 4,
|
|
PM_QID_CLOCK_GET_ATTRIBUTES = 5,
|
|
PM_QID_PINCTRL_GET_NUM_PINS = 6,
|
|
PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
|
|
PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
|
|
PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
|
|
PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
|
|
PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
|
|
PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
|
|
PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
|
|
};
|
|
|
|
#define PM_SIP_SVC 0xc2000000
|
|
|
|
#define ZYNQMP_PM_VERSION_MAJOR 1
|
|
#define ZYNQMP_PM_VERSION_MINOR 0
|
|
#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
|
|
#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
|
|
|
|
#define ZYNQMP_PM_VERSION \
|
|
((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
|
|
ZYNQMP_PM_VERSION_MINOR)
|
|
|
|
#define ZYNQMP_PM_VERSION_INVALID ~0
|
|
|
|
#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
|
|
|
|
/*
|
|
* Return payload size
|
|
* Not every firmware call expects the same amount of return bytes, however the
|
|
* firmware driver always copies 5 bytes from RX buffer to the ret_payload
|
|
* buffer. Therefore allocating with this defined value is recommended to avoid
|
|
* overflows.
|
|
*/
|
|
#define PAYLOAD_ARG_CNT 5U
|
|
|
|
unsigned int zynqmp_firmware_version(void);
|
|
void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
|
|
int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
|
|
u32 arg3, u32 *ret_payload);
|
|
|
|
#endif /* _ZYNQMP_FIRMWARE_H_ */
|