mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-12 07:43:22 +09:00
![Mike Frysinger](/assets/img/avatar_default.png)
Recent builds for SH4 boards fail with a lot of errors like: cmd_mem.o: In function 'dcache_invalid_range': include/asm/cache.h:25: multiple definition of 'dcache_invalid_range' include/asm/cache.h:25: first defined here This is due to the funcs being defined in the header, but not static or inline or extern. So move them to the sh4-specific cache.c file. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
35 lines
764 B
C
35 lines
764 B
C
#ifndef __ASM_SH_CACHE_H
|
|
#define __ASM_SH_CACHE_H
|
|
|
|
#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
|
|
|
|
int cache_control(unsigned int cmd);
|
|
|
|
#define L1_CACHE_BYTES 32
|
|
|
|
struct __large_struct { unsigned long buf[100]; };
|
|
#define __m(x) (*(struct __large_struct *)(x))
|
|
|
|
void dcache_wback_range(u32 start, u32 end);
|
|
void dcache_invalid_range(u32 start, u32 end);
|
|
|
|
#else
|
|
|
|
/*
|
|
* 32-bytes is the largest L1 data cache line size for SH the architecture. So
|
|
* it is a safe default for DMA alignment.
|
|
*/
|
|
#define ARCH_DMA_MINALIGN 32
|
|
|
|
#endif /* CONFIG_SH4 || CONFIG_SH4A */
|
|
|
|
/*
|
|
* Use the L1 data cache line size value for the minimum DMA buffer alignment
|
|
* on SH.
|
|
*/
|
|
#ifndef ARCH_DMA_MINALIGN
|
|
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
|
|
#endif
|
|
|
|
#endif /* __ASM_SH_CACHE_H */
|