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![Stephen Warren](/assets/img/avatar_default.png)
Clean up the naming of pinmux-related objects: * Refer to drive groups rather than pad groups to match the Linux kernel. * Ensure all pinmux API types are prefixed with pmux_, values (defines) are prefixed with PMUX_, and functions prefixed with pinmux_. * Modify a few type names to make their content clearer. * Minimal changes to SoC-specific .h/.c files are made so the code still compiles. A separate per-SoC change will be made immediately following, in order to keep individual patch size down. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
392 lines
8.1 KiB
C
392 lines
8.1 KiB
C
/*
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* (C) Copyright 2013
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA124_PINMUX_H_
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#define _TEGRA124_PINMUX_H_
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/*
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* Pin groups which we adjust. There are three basic attributes of each pin
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* group which use this enum:
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*
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* - function
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* - pullup / pulldown
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* - tristate or normal
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*/
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enum pmux_pingrp {
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PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
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PINGRP_ULPI_DATA1,
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PINGRP_ULPI_DATA2,
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PINGRP_ULPI_DATA3,
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PINGRP_ULPI_DATA4,
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PINGRP_ULPI_DATA5,
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PINGRP_ULPI_DATA6,
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PINGRP_ULPI_DATA7,
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PINGRP_ULPI_CLK,
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PINGRP_ULPI_DIR,
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PINGRP_ULPI_NXT,
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PINGRP_ULPI_STP,
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PINGRP_DAP3_FS,
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PINGRP_DAP3_DIN,
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PINGRP_DAP3_DOUT,
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PINGRP_DAP3_SCLK,
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PINGRP_GPIO_PV0,
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PINGRP_GPIO_PV1,
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PINGRP_SDMMC1_CLK,
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PINGRP_SDMMC1_CMD,
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PINGRP_SDMMC1_DAT3,
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PINGRP_SDMMC1_DAT2,
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PINGRP_SDMMC1_DAT1,
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PINGRP_SDMMC1_DAT0,
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PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
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PINGRP_CLK2_REQ,
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PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
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PINGRP_DDC_SCL,
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PINGRP_DDC_SDA,
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PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
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PINGRP_UART2_TXD,
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PINGRP_UART2_RTS_N,
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PINGRP_UART2_CTS_N,
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PINGRP_UART3_TXD,
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PINGRP_UART3_RXD,
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PINGRP_UART3_CTS_N,
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PINGRP_UART3_RTS_N,
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PINGRP_GPIO_PU0,
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PINGRP_GPIO_PU1,
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PINGRP_GPIO_PU2,
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PINGRP_GPIO_PU3,
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PINGRP_GPIO_PU4,
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PINGRP_GPIO_PU5,
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PINGRP_GPIO_PU6,
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PINGRP_GEN1_I2C_SDA,
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PINGRP_GEN1_I2C_SCL,
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PINGRP_DAP4_FS,
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PINGRP_DAP4_DIN,
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PINGRP_DAP4_DOUT,
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PINGRP_DAP4_SCLK,
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PINGRP_CLK3_OUT,
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PINGRP_CLK3_REQ,
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/* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */
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PINGRP_GPIO_PC7, /* offset 0x31c0 */
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PINGRP_GPIO_PI5,
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PINGRP_GPIO_PI7,
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PINGRP_GPIO_PK0,
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PINGRP_GPIO_PK1,
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PINGRP_GPIO_PJ0,
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PINGRP_GPIO_PJ2,
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PINGRP_GPIO_PK3,
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PINGRP_GPIO_PK4,
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PINGRP_GPIO_PK2,
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PINGRP_GPIO_PI3,
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PINGRP_GPIO_PI6,
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PINGRP_GPIO_PG0,
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PINGRP_GPIO_PG1,
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PINGRP_GPIO_PG2,
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PINGRP_GPIO_PG3,
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PINGRP_GPIO_PG4,
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PINGRP_GPIO_PG5,
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PINGRP_GPIO_PG6,
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PINGRP_GPIO_PG7,
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PINGRP_GPIO_PH0,
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PINGRP_GPIO_PH1,
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PINGRP_GPIO_PH2,
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PINGRP_GPIO_PH3,
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PINGRP_GPIO_PH4,
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PINGRP_GPIO_PH5,
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PINGRP_GPIO_PH6,
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PINGRP_GPIO_PH7,
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PINGRP_GPIO_PJ7,
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PINGRP_GPIO_PB0,
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PINGRP_GPIO_PB1,
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PINGRP_GPIO_PK7,
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PINGRP_GPIO_PI0,
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PINGRP_GPIO_PI1,
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PINGRP_GPIO_PI2,
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PINGRP_GPIO_PI4, /* offset 0x324c */
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PINGRP_GEN2_I2C_SCL,
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PINGRP_GEN2_I2C_SDA,
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PINGRP_SDMMC4_CLK,
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PINGRP_SDMMC4_CMD,
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PINGRP_SDMMC4_DAT0,
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PINGRP_SDMMC4_DAT1,
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PINGRP_SDMMC4_DAT2,
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PINGRP_SDMMC4_DAT3,
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PINGRP_SDMMC4_DAT4,
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PINGRP_SDMMC4_DAT5,
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PINGRP_SDMMC4_DAT6,
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PINGRP_SDMMC4_DAT7,
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PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
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PINGRP_GPIO_PCC1,
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PINGRP_GPIO_PBB0,
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PINGRP_CAM_I2C_SCL,
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PINGRP_CAM_I2C_SDA,
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PINGRP_GPIO_PBB3,
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PINGRP_GPIO_PBB4,
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PINGRP_GPIO_PBB5,
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PINGRP_GPIO_PBB6,
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PINGRP_GPIO_PBB7,
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PINGRP_GPIO_PCC2,
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PINGRP_JTAG_RTCK,
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PINGRP_PWR_I2C_SCL,
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PINGRP_PWR_I2C_SDA,
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PINGRP_KB_ROW0,
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PINGRP_KB_ROW1,
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PINGRP_KB_ROW2,
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PINGRP_KB_ROW3,
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PINGRP_KB_ROW4,
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PINGRP_KB_ROW5,
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PINGRP_KB_ROW6,
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PINGRP_KB_ROW7,
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PINGRP_KB_ROW8,
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PINGRP_KB_ROW9,
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PINGRP_KB_ROW10,
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PINGRP_KB_ROW11,
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PINGRP_KB_ROW12,
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PINGRP_KB_ROW13,
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PINGRP_KB_ROW14,
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PINGRP_KB_ROW15,
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PINGRP_KB_COL0, /* offset 0x32fc */
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PINGRP_KB_COL1,
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PINGRP_KB_COL2,
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PINGRP_KB_COL3,
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PINGRP_KB_COL4,
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PINGRP_KB_COL5,
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PINGRP_KB_COL6,
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PINGRP_KB_COL7,
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PINGRP_CLK_32K_OUT,
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PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2, /* offset 0x3324 */
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PINGRP_CPU_PWR_REQ,
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PINGRP_PWR_INT_N,
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PINGRP_CLK_32K_IN,
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PINGRP_OWR,
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PINGRP_DAP1_FS,
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PINGRP_DAP1_DIN,
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PINGRP_DAP1_DOUT,
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PINGRP_DAP1_SCLK,
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PINGRP_CLK1_REQ,
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PINGRP_CLK1_OUT,
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PINGRP_SPDIF_IN,
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PINGRP_SPDIF_OUT,
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PINGRP_DAP2_FS,
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PINGRP_DAP2_DIN,
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PINGRP_DAP2_DOUT,
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PINGRP_DAP2_SCLK,
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PINGRP_DVFS_PWM,
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PINGRP_GPIO_X1_AUD,
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PINGRP_GPIO_X3_AUD,
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PINGRP_DVFS_CLK,
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PINGRP_GPIO_X4_AUD,
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PINGRP_GPIO_X5_AUD,
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PINGRP_GPIO_X6_AUD,
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PINGRP_GPIO_X7_AUD,
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PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
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PINGRP_SDMMC3_CMD,
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PINGRP_SDMMC3_DAT0,
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PINGRP_SDMMC3_DAT1,
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PINGRP_SDMMC3_DAT2,
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PINGRP_SDMMC3_DAT3,
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PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */
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PINGRP_PEX_L0_CLKREQ,
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PINGRP_PEX_WAKE,
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PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2,
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PINGRP_PEX_L1_CLKREQ,
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PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */
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PINGRP_SDMMC1_WP_N,
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PINGRP_SDMMC3_CD_N,
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PINGRP_GPIO_W2_AUD,
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PINGRP_GPIO_W3_AUD,
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PINGRP_USB_VBUS_EN0,
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PINGRP_USB_VBUS_EN1,
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PINGRP_SDMMC3_CLK_LB_IN,
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PINGRP_SDMMC3_CLK_LB_OUT,
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PINGRP_GMI_CLK_LB,
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PINGRP_RESET_OUT_N,
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PINGRP_KB_ROW16, /* offset 0x340c */
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PINGRP_KB_ROW17,
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PINGRP_USB_VBUS_EN2,
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PINGRP_GPIO_PFF2,
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PINGRP_DP_HPD, /* last reg offset = 0x3430 */
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PMUX_PINGRP_COUNT,
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};
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enum pmux_drvgrp {
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PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
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PDRIVE_PINGROUP_AO2,
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PDRIVE_PINGROUP_AT1,
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PDRIVE_PINGROUP_AT2,
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PDRIVE_PINGROUP_AT3,
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PDRIVE_PINGROUP_AT4,
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PDRIVE_PINGROUP_AT5,
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PDRIVE_PINGROUP_CDEV1,
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PDRIVE_PINGROUP_CDEV2,
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PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
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PDRIVE_PINGROUP_DAP2,
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PDRIVE_PINGROUP_DAP3,
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PDRIVE_PINGROUP_DAP4,
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PDRIVE_PINGROUP_DBG,
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PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
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PDRIVE_PINGROUP_SPI,
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PDRIVE_PINGROUP_UAA,
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PDRIVE_PINGROUP_UAB,
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PDRIVE_PINGROUP_UART2,
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PDRIVE_PINGROUP_UART3,
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PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
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PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
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PDRIVE_PINGROUP_GMA,
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PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
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PDRIVE_PINGROUP_GMF,
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PDRIVE_PINGROUP_GMG,
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PDRIVE_PINGROUP_GMH,
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PDRIVE_PINGROUP_OWR,
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PDRIVE_PINGROUP_UAD,
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PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
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PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
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PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
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PDRIVE_PINGROUP_DAP5,
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PDRIVE_PINGROUP_VBUS,
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PDRIVE_PINGROUP_AO3,
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PDRIVE_PINGROUP_HVC,
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PDRIVE_PINGROUP_SDIO4,
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PDRIVE_PINGROUP_AO0,
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PMUX_DRVGRP_COUNT,
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};
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/*
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* Functions which can be assigned to each of the pin groups. The values here
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* bear no relation to the values programmed into pinmux registers and are
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* purely a convenience. The translation is done through a table search.
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*/
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enum pmux_func {
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PMUX_FUNC_AHB_CLK,
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PMUX_FUNC_APB_CLK,
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PMUX_FUNC_AUDIO_SYNC,
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PMUX_FUNC_CRT,
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PMUX_FUNC_DAP1,
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PMUX_FUNC_DAP2,
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PMUX_FUNC_DAP3,
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PMUX_FUNC_DAP4,
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PMUX_FUNC_DAP5,
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PMUX_FUNC_DISPA,
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PMUX_FUNC_DISPB,
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PMUX_FUNC_EMC_TEST0_DLL,
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PMUX_FUNC_EMC_TEST1_DLL,
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PMUX_FUNC_GMI,
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PMUX_FUNC_GMI_INT,
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PMUX_FUNC_HDMI,
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PMUX_FUNC_I2C1,
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PMUX_FUNC_I2C2,
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PMUX_FUNC_I2C3,
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PMUX_FUNC_IDE,
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PMUX_FUNC_KBC,
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PMUX_FUNC_MIO,
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PMUX_FUNC_MIPI_HS,
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PMUX_FUNC_NAND,
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PMUX_FUNC_OSC,
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PMUX_FUNC_OWR,
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PMUX_FUNC_PCIE,
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PMUX_FUNC_PLLA_OUT,
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PMUX_FUNC_PLLC_OUT1,
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PMUX_FUNC_PLLM_OUT1,
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PMUX_FUNC_PLLP_OUT2,
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PMUX_FUNC_PLLP_OUT3,
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PMUX_FUNC_PLLP_OUT4,
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PMUX_FUNC_PWM,
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PMUX_FUNC_PWR_INTR,
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PMUX_FUNC_PWR_ON,
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PMUX_FUNC_RTCK,
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PMUX_FUNC_SDMMC1,
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PMUX_FUNC_SDMMC2,
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PMUX_FUNC_SDMMC3,
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PMUX_FUNC_SDMMC4,
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PMUX_FUNC_SFLASH,
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PMUX_FUNC_SPDIF,
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PMUX_FUNC_SPI1,
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PMUX_FUNC_SPI2,
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PMUX_FUNC_SPI2_ALT,
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PMUX_FUNC_SPI3,
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PMUX_FUNC_SPI4,
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PMUX_FUNC_TRACE,
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PMUX_FUNC_TWC,
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PMUX_FUNC_UARTA,
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PMUX_FUNC_UARTB,
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PMUX_FUNC_UARTC,
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PMUX_FUNC_UARTD,
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PMUX_FUNC_UARTE,
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PMUX_FUNC_ULPI,
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PMUX_FUNC_VI,
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PMUX_FUNC_VI_SENSOR_CLK,
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PMUX_FUNC_XIO,
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/* End of Tegra2 MUX selectors */
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PMUX_FUNC_BLINK,
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PMUX_FUNC_CEC,
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PMUX_FUNC_CLK12,
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PMUX_FUNC_DAP,
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PMUX_FUNC_DAPSDMMC2,
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PMUX_FUNC_DDR,
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PMUX_FUNC_DEV3,
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PMUX_FUNC_DTV,
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PMUX_FUNC_VI_ALT1,
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PMUX_FUNC_VI_ALT2,
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PMUX_FUNC_VI_ALT3,
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PMUX_FUNC_EMC_DLL,
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PMUX_FUNC_EXTPERIPH1,
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PMUX_FUNC_EXTPERIPH2,
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PMUX_FUNC_EXTPERIPH3,
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PMUX_FUNC_GMI_ALT,
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PMUX_FUNC_HDA,
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PMUX_FUNC_HSI,
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PMUX_FUNC_I2C4,
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PMUX_FUNC_I2C5,
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PMUX_FUNC_I2CPWR,
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PMUX_FUNC_I2S0,
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PMUX_FUNC_I2S1,
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PMUX_FUNC_I2S2,
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PMUX_FUNC_I2S3,
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PMUX_FUNC_I2S4,
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PMUX_FUNC_NAND_ALT,
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PMUX_FUNC_POPSDIO4,
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PMUX_FUNC_POPSDMMC4,
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PMUX_FUNC_PWM0,
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PMUX_FUNC_PWM1,
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PMUX_FUNC_PWM2,
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PMUX_FUNC_PWM3,
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PMUX_FUNC_SATA,
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PMUX_FUNC_SPI5,
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PMUX_FUNC_SPI6,
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PMUX_FUNC_SYSCLK,
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PMUX_FUNC_VGP1,
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PMUX_FUNC_VGP2,
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PMUX_FUNC_VGP3,
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PMUX_FUNC_VGP4,
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PMUX_FUNC_VGP5,
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PMUX_FUNC_VGP6,
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/* End of Tegra3 MUX selectors */
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PMUX_FUNC_USB,
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PMUX_FUNC_SOC,
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PMUX_FUNC_CPU,
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PMUX_FUNC_CLK,
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PMUX_FUNC_PWRON,
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PMUX_FUNC_PMI,
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PMUX_FUNC_CLDVFS,
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PMUX_FUNC_RESET_OUT_N,
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/* End of Tegra114 MUX selectors */
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PMUX_FUNC_COUNT,
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PMUX_FUNC_INVALID = 0x4000,
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PMUX_FUNC_RSVD1 = 0x8000,
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PMUX_FUNC_RSVD2 = 0x8001,
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PMUX_FUNC_RSVD3 = 0x8002,
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PMUX_FUNC_RSVD4 = 0x8003,
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};
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#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
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#define TEGRA_PMX_HAS_RCV_SEL
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#define TEGRA_PMX_HAS_DRVGRPS
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#include <asm/arch-tegra/pinmux.h>
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#endif /* _TEGRA124_PINMUX_H_ */
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